SDRAM having posted CAS function of JEDEC standard

Details SDRAM having posted CAS function of JEDEC standard SDRAM having posted CAS function of JEDEC standard

2001-05-02

2002-11-19

Zarabian, Amir (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

06483769

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to semiconductor devices and, in particular, to a synchronous dynamic random access memory (SDRAM) operating in synchronization with a clock signal.
2. Description of Related Art
Generally, a read operation or a write operation of a synchronous dynamic random access memory (SDPAM) is controlled in synchronization with a clock signal applied external of the memory chip. In a DRAM, a column address strobe (CAS) command, such as a write command or a read command, can be provided a predetermined time after a row address strobe (RAS) activation command is provided. This predetermined time is referred to as a RAS to CAS delay (tRCD). That is, a read command or a write command can be provided a tRCD after an RAS activation command. In an SDRAM, a tRCD generally takes two or three clock cycles. Since a clock cycle is represented by a tCC, the tRCD is two or three tCC.
Therefore, in a conventional SDRAM, considering a tRCD, the controller for the SDRAM should provide a read command or a write command at an appropriate time after an RAS activation command. In this conventional method, the controller for an SDRAM or a user should consider the tRCD specification of the SDRAM, and the decrease in usage efficiency of a bus between the controller and the SDRAM command input pins. Due to these problems, an international electronics standardization organization, namely the Joint Electronic Device Engineering Council (JEDEC), proposed to add a CAS latency function (also referred to as a posted CAS function) and set up a standard corresponding thereto. JEDEC proposes a posted CAS function in a double data rate
2
(DDR
2
) SDRAM, which is an upgraded version of a DDR SDRAM. Also, the proposed JEDEC standards require that the tCC for an additive CAS latency be set in advance using an extended mode register set (EMRS) of an SDRAM.
SUMMARY OF THE INVENTION
The problems stated above, as well as other related problems of the prior art, are solved by the present invention, a synchronous semiconductor memory device having a posted column address strobe (CAS) function. The present invention provides an SDRAM that enhances the usage efficiency of a bus between the SDRAM and an external controller, and satisfies the posted CAS function requirement promulgated by JEDEC.
According to an aspect of the invention, there is provided a synchronous semiconductor memory device having a posted column address. strobe (CAS) function. The synchronous semiconductor memory device includes one or more command input pins for receiving command signals applied externally with respect to the memory device. A command decoder receives the command signals and outputs decoded commands corresponding to the command signals. A write command latency control unit receives a write command from among the decoded commands output from the command decoder, delays the write command for a time period equal to N/2 times a clock signal cycle in response to a predetermined latency control signal, and outputs the delayed write command. N is an integer equal to or greater than zero. The predetermined latency control signal is activated in response to a value set in an extended mode register set of the memory device.
According to another aspect of the invention, there is provided a synchronous semiconductor memory device having a posted column address strobe (CAS) function. The synchronous semiconductor memory device includes one or more command input pins adapted to receive command signals applied externally with respect to the memory device. A command decoder receives the command signals and outputs decoded commands corresponding to the command signals. A read command latency control unit receives a read command from among the decoded commands output from the command decoder, delays the read command for a time period equal to N/2 times a clock signal cycle in response to a predetermined latency control signal, and outputs the delayed read command. N is an integer equal to or greater than zero. The predetermined latency control signal is activated in response to a value set in an extended mode register set.
According to yet another aspect of the invention, there is provided a synchronous semiconductor memory device having a posted column address strobe (CAS) function. The synchronous semiconductor memory device includes one or more address input pins adapted to receive an address signal applied externally with respect to the memory device. A column address determining unit receives the address signal, and outputs the address signal to a column address path when the address signal is a column address signal. A column address latency control unit, located on the column address path, delays the column address signal for a time period equal to N/2 times a clock signal cycle in response to a predetermined latency control signal, and outputs the delayed column address signal. N is an integer equal to or greater than zero. The predetermined latency control signal is activated in response to a value set in an extended mode register set.
According to yet still another aspect of the invention, there is provided a synchronous semiconductor memory device having a posted column address strobe (CAS) function. The synchronous semiconductor memory device includes one or more command input pins adapted to receive command signals applied from the outside. A command decoder receives the command signals and outputs decoded commands corresponding to the command signals. A write command latency control unit receives a write command from among the decoded commands output from the command decoder, delays the write command for a time period equal to N/2 times a clock signal cycle in response to a predetermined latency control signal, and outputs the delayed write command. A read command latency control receives a read command from among the decoded commands output from the command decoder, delays the read command for a time period equal to N/2 times the clock signal cycle in response to the predetermined latency control signal, and outputs the delayed read command. N is an integer equal to or greater than zero. The predetermined latency control signal is activated in response to a value set in an extended mode register set.
According to a further aspect of the invention, there is provided a synchronous semiconductor memory device having a posted column address strobe (CAS) function. The synchronous semiconductor memory device includes one or more command input pins for receiving command signals applied externally with respect to the memory device. One or more address input pins receive an address signal applied externally with respect to the memory device. A command decoder receives the command signals and outputs decoded commands corresponding to the command signals. A write command latency control unit receives a write command from among the decoded commands output from the command decoder, delays the write command for a time period equal to N/2 times a clock signal cycle in response to a predetermined latency control signal, and outputs the delayed write command. A read command latency control unit receives a read command from among the decoded commands output from the command decoder, delays the read command for the time period equal to N/2 times the clock signal cycle in response to the predetermined latency control signal, and outputs the delayed read command. A column address determining unit receives the address signal, and outputs the address signal to a column address path when the address signal is a column address signal. A column address latency control unit, located on the column address path, delays the column address signal for the time period equal to N/2 times the clock signal cycle in response to the predetermined latency control signal, and outputs the delayed column address signal. N is an integer one of equal to and greater than zero. The predetermined latency control signal is activated in response to a value set in an extended mode register set.
These and other aspects,

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