Self reset clock buffer in memory devices

Details Self reset clock buffer in memory devices Self reset clock buffer in memory devices

2011-08-16

2011-08-16

Dinh, Son T (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230080, C365S233110

Reexamination Certificate

active

08000165

ABSTRACT:
A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least one of the logic gates. The cross-coupled logic circuit is coupled to an input for accepting a clock signal. The memory device also includes a clock driver operable to generate a clock signal from the output of the cross-coupled logic circuit. A feedback loop from the clock signal to the cross-coupled logic circuit controls the cross-coupled logic circuit. A buffer circuit including a tri-state inverter is coupled to the clock signal to maintain the clock signal while avoiding contention with the clock generator. The memory device is enabled by a chip select signal.

REFERENCES:
patent: 6222791 (2001-04-01), Becker et al.
patent: 6329867 (2001-12-01), Penney et al.
patent: 7002875 (2006-02-01), Ikeda
patent: 7116150 (2006-10-01), Francom
patent: 7522469 (2009-04-01), Lee
patent: 7646658 (2010-01-01), Chen et al.
patent: 2005/0281129 (2005-12-01), Ikeda
International Search Report and Written Opinion—PCT/US2009/056026, International Search Authority—European Patent Office—Mar. 9, 2010.

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