Memory array leakage reduction circuit and method

Memory cell array biasing method and a semiconductor memory...

Memory cell array biasing method and a semiconductor memory...

Memory cell array having compact word line arrangement

Memory cell decoder not including a charge pump

Memory cell of non-volatile semiconductor memory device

Memory cell of nonvolatile semiconductor memory device

Memory cell with known state on power-up

Memory cell with user-selectable logic state on power-up

Memory circuit including word line reset circuit and method...

Memory circuit sequentially accessible by arbitrary address

Memory circuits having different word line driving circuit...

Memory circuits having different word line driving circuit...

Memory component and addressing of memory cells

Memory comprising simultaneously addressable memory elements

Memory control circuit reducing a consumed power of memory

Memory control system for controlling write-enable signals

Memory control with dynamic driver disabling

Memory controller for using reserved dram addresses for expanded

Memory decoder with zero static power