Memory circuit including word line reset circuit and method...

Details Memory circuit including word line reset circuit and method... Memory circuit including word line reset circuit and method...

2000-04-19

2001-07-17

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189080

Reexamination Certificate

active

06262934

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory circuit, and more particularly relates to a word line reset circuit for a semiconductor memory circuit and a word line reset method.
2. Description of the Related Art
FIG. 3
is a partial circuit diagram of a semiconductor memory circuit. As shown in
FIG. 3
, a large number of memory cells
10
(only some of which are shown in
FIG. 3
, with the remainder being omitted) are arrayed horizontally and vertically, so as to comprise a memory cell array
12
. The memory cell array
12
is arranged in a grid, with word lines
14
and bit lines
16
at right-angles with respect to each other. Each memory cell
10
is then connected to one word line
14
and one bit line
16
.
In the case of the one transistor, one capacitor-type DRAM memory cell
10
shown in
FIG. 3
, a transistor gate is connected to a word line
14
and another terminal of the transistor is connected to a bit line
16
. Word line driver circuits (hereinafter referred to as word line reset circuits)
18
are connected to the word lines
14
. A word line reset circuit
18
selects one of the word lines
14
and applies an H-level potential to the selected word line
14
. This turns the transistor of the memory cell
10
connected to the selected word line
14
on and the charge of a capacitor is transmitted to the bit line
16
. On the other hand, L-level potentials are applied to word lines that are not selected. As a result, transistors of memory cells
10
connected to unselected word lines
14
are off and capacitor charge is held without being transmitted to the bit lines
16
.
When another word line
14
is then subsequently selected, it is necessary to make the H-level of the previously selected word line an L-level. This operation is referred to as a “reset”, and in related memory circuits this is achieved by connecting previously selected word lines
14
to an earth supply line at an L-level.
If a connected word line
14
is put to ground, a transistor of a memory cell
10
is turned off. However, the potential of the earth line temporarily rises because the charge on the selected word line flows to the earth supply line due to this reset operation. This situation is referred to as the occurrence of noise, and in this case the potential of non-selected word lines temporarily rises above ground. This results in the problem of charge leaking to bit lines from capacitors of memory cells
10
connected to unselected word lines. Ways of making the potential of unselected word lines lower than ground are disclosed in Japanese Patent Laid-open Publication Nos. Hei. 9-134591 and 11-250655, and U.S. Pat. Nos. 5,617,367 and 5,410,508.
However, even if the level of unselected word lines is set to a lower level than ground, noise occurs when the word lines are reset and charge accumulated at the capacitors of the memory cells leaks.
SUMMARY OF THE INVENTION
It is therefore the object of the invention to provide a memory circuit including a word line reset circuit where the occurrence of noise at the time of resetting word lines is lowered and leaking of charge from memory cells connected to unselected word lines is reduced.
In order to achieve the aforementioned object, a memory circuit of the invention comprises a memory cell array having word lines, bit lines and memory cells each connected to one of the word lines and one of the bit lines, and a word line reset circuit connected to one of the word lines for applying a word line activation level when the connected word line is selected, and for applying a lower level which is lower than a word line deactivation level to the connected word line when the connected word line is not selected. The word line reset circuit comprises a first driver circuit for applying the word line activation level to the connected word line during a first select period where the connected word line is selected, a second driver circuit for applying the word line deactivation level to the connected word line during a second select period starting after the first select period where the connected word line is selected, and a third driver circuit for applying the lower level to the connected word line during a period other than the first and second select periods.
Various embodiments of the present invention have been shown in brief. However, the various embodiments of the present invention and specific configurations of these embodiments will be understood from the following description.


REFERENCES:
patent: 4581722 (1986-04-01), Takemae
patent: 4628486 (1986-12-01), Sakui
patent: 5257238 (1993-10-01), Lee et al.
patent: 5410508 (1995-04-01), McLaury
patent: 5416747 (1995-05-01), Ohira
patent: 5519665 (1996-05-01), Chishiki
patent: 5617369 (1997-04-01), Tomishima et al.
patent: 0 559 995 A1 (1993-09-01), None
patent: 08087884 (1996-04-01), None
patent: 09073789 (1997-03-01), None
patent: 10283778 (1998-10-01), None
patent: 11250655 (1999-09-01), None

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