Memory cell array having compact word line arrangement

Details Memory cell array having compact word line arrangement Memory cell array having compact word line arrangement

1994-09-06

1996-04-09

Popek, Joseph A.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, 365 63, G11C 800

Patent

active

055068162

ABSTRACT:
A semiconductor memory array having a plurality of rows of memory cells, a word line, which extends into at least two memory blocks, to carry drive signals, such as read select and deselect signals, erase select and deselect signals, and program select and deselect signals for selective delivery to a subword line. Two pairs of subword lines and associated drivers are arranged with each pair selectively connectible to a portion of the word line within the block containing the subword line pair and to an associated set of memory cells. Each subword line driver selectively delivers drive signals from the word line to a respective, selected one of the subword lines. The subword lines and their drivers are arranged to extend from opposite sides into the block with which the subword line pairs are associated to reduce the layout size necessary, and to enable fewer word line drivers to be needed for a particular layout pitch. A subword line driver (SWD) circuit has an NMOS transistor and a PMOS transistor, with the drain of the NMOS transistor and the source of the PMOS transistor connected to the word line, and the source of the NMOS transistor and the drain of the PMOS transistor connected to receive a word line selection signal from a common source line. The gate of the NMOS transistor is connected to a block select line that carries a "true" block select signal, and the gate of the PMOS transistor is connected to a block select line that carries a complement block signal.

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