Memory cell array biasing method and a semiconductor memory...

Details Memory cell array biasing method and a semiconductor memory... Memory cell array biasing method and a semiconductor memory...

2008-01-08

2008-01-08

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230010

Reexamination Certificate

active

11327967

ABSTRACT:
A method of biasing a memory cell array during a data writing operation and a semiconductor memory device are provided. The semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.

REFERENCES:
patent: 4455629 (1984-06-01), Suzuki et al.
patent: 4598386 (1986-07-01), Roesner et al.
patent: 4884238 (1989-11-01), Lee et al.
patent: 5751651 (1998-05-01), Ooishi
patent: 5818749 (1998-10-01), Harshfield
patent: 6084804 (2000-07-01), McPartland
patent: 6144610 (2000-11-01), Zheng et al.
patent: 6337831 (2002-01-01), Nam
patent: 6452858 (2002-09-01), Hanzawa et al.
patent: 6462984 (2002-10-01), Xu et al.
patent: 6618295 (2003-09-01), Scheuerlein
patent: 2003/0123284 (2003-07-01), Lowry et al.
patent: 2006/0203541 (2006-09-01), Toda
patent: 2003-0059436 (2003-07-01), None
patent: 2003-0070544 (2003-08-01), None
Toshihiko Hirose, et al: “A 20-ns 4-Mb CMOS SRAM with Hierarchical Word Decoding Architecture” IEEE Journal of Solid-State Circuits, IEEE Service Center, Piscataway, NJ, US, vol. 25, No. 5, (Oct. 1, 1990), pp. 1068-1073.

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