Ram row decode circuitry that utilizes a precharge circuit that

RAM variable size block write

Random access memory word line select circuit having rapid dynam

Read circuit for magnetic memory array using magnetic tunnel jun

Read operation for non-volatile storage with compensation...

Read/write memory with plural memory cell write capability at a

Reduced area word line driving circuit for random access memory

Reduced delay address decoders and decoding methods for...

Reduced latency row selection circuit and method

Reduced leakage driver circuit and memory device employing same

Reduced line select decoder for a memory array

Redundancy architecture and method for non-volatile storage

Redundancy decoding circuit having automatic deselection

Redundancy decoding circuit using n-channel transistors

Redundancy semiconductor memory device which utilizes spare memo

Redundant semiconductor memory device using a single now address

Repeater with threshold modulation

Reversible polarity decoder circuit

Reversible-polarity decoder circuit and method

Roll call decoder for semiconductor memory having redundant memo