Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2008-05-27
2008-05-27
Elms, Richard T. (Department: 2824)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S194000, C365S185130
Reexamination Certificate
active
11247945
ABSTRACT:
Memory circuits having different configurations of local word line driving circuits (LWLDC) and methods for designing such circuits are provided. The memory circuits include an array of memory cells and a plurality of local word lines each coupled to a different subset of the array of memory cells. The memory circuit further includes a plurality of LWLDC respectively coupled to the plurality of local word lines, a global word line bus coupled to the plurality of LWLDC, and a global word line driving circuit (GWLDC) coupled to the global word line bus. At least one of the plurality of LWLDC may be configured to have a smaller amount of load capacitance than another LWLDC arranged comparatively farther from the GWLDC. In some embodiments, the variance of load capacitance may be induced by a variance of size among the plurality of LWLDC, specifically with reference to different transistor width dimensions.
REFERENCES:
patent: 5596286 (1997-01-01), Houston
patent: 5602785 (1997-02-01), Casper
patent: 5724292 (1998-03-01), Wada
patent: 5917365 (1999-06-01), Houston
patent: 6501696 (2002-12-01), Mnich et al.
patent: 6538932 (2003-03-01), Ellis et al.
patent: 6768143 (2004-07-01), Fredeman et al.
patent: 2005/0195672 (2005-09-01), Lee
Seevinck et al., “Current Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM's,” IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, pp. 525-536.
Wong et al., “Design and modeling of tapered LWL architecture for high density SRAM,” © 2004 IEEE, 3 pages.
U.S. Appl. No. 11/303,067, filed Dec. 14, 2005.
U.S. Appl. No. 11/262,412, filed Oct. 28, 2005.
U.S. Appl. No. 60/648,333, filed Jan. 28, 2005.
U.S. Appl. No. 11/380,333, filed Apr. 26, 2006.
U.S. Appl. No. 11/259,342, filed Oct. 24, 2005.
U.S. Appl. No. 10/870,289, filed Jun. 16, 2004.
U.S. Appl. No. 10/873,608, filed Jun. 29, 2004.
Cypress Semiconductor Corp.
Daffer Kevin L.
Daffer McDaniel LLP
Elms Richard T.
Wendler Eric
LandOfFree
Memory circuits having different word line driving circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory circuits having different word line driving circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory circuits having different word line driving circuit... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3924538