Memory component and addressing of memory cells

Details Memory component and addressing of memory cells Memory component and addressing of memory cells

2005-12-09

2008-03-25

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S200000

Reexamination Certificate

active

07349286

ABSTRACT:
A memory component comprises a plurality of memory cells that are each assigned an address, and an address memory for storing numerical values which are uniquely related to addresses of defective memory cells. An address converter having an input for receiving a first address and an output for outputting a second address is designed in such a way that the second address output at its output is dependent on the first address received at its input and on the numerical values stored in the address memory, each first address being uniquely assigned a second address. An address bus, which is connected to the output of the address converter, transfers the second address to an input of an address decoder, which is designed for selecting a memory cell to which the second address is assigned.

REFERENCES:
patent: 5848006 (1998-12-01), Nagata
patent: 5886941 (1999-03-01), Tomita
patent: 6144612 (2000-11-01), Numasawa
patent: 6243319 (2001-06-01), Yokozeki
patent: 2002/0122337 (2002-09-01), Kanazawa et al.
patent: 10127194 (2002-12-01), None

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