Memory controller for using reserved dram addresses for expanded

Details Memory controller for using reserved dram addresses for expanded Memory controller for using reserved dram addresses for expanded

1989-11-13

1991-01-15

Bowler, Alyssa H.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, 365233, 36518908, 36523002, G11C 700, G11C 11407, G11C 11408

Patent

active

049858718

ABSTRACT:
A memory controller which can map expanded memory space (EMS) addresses into the dynamic random access memory (DRAM) behind video random access memory (RAM) addresses or other reserved areas of memory. A single chip has both a DRAM decoder and an EMS decoder operating in parallel. A DRAM decoder examines received addresses and provides an enable signal to a DRAM timing circuit if the address is within the DRAM range and not for a reserved group of addresses. A separate EMS decoder provides a translated address when a received address is within an EMS window. The EMS decoder also provides an EMS timing signal to the DRAM timing circuit.

REFERENCES:
patent: 4758996 (1988-07-01), Goldman
patent: 4763302 (1988-08-01), Yamada
patent: 4773049 (1988-09-01), Takemae
patent: 4802135 (1989-01-01), Shinoda et al.
patent: 4896294 (1990-01-01), Shimizu et al.
patent: 4899272 (1990-02-01), Fung et al.

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