Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent
1997-11-07
1999-09-07
Nelms, David
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
3652385, G11C 800
Patent
active
059497360
ABSTRACT:
A memory control circuit comprises a memory composed of eight DRAMs and coupled to a data bus having a but width of eight bytes, and a memory controller which is coupled through the data bus to the memory and which supplies a memory address, a write enable signal and a column address strobe signal to the memory. A CPU is coupled to the memory controller for controlling the memory controller, and generates a plurality of byte enable signals corresponding to the eight DRAMs in a one-to-one relation, respectively. A row address strobe control circuit receives a memory cycle start signal from the memory controller and the byte enable signals from the CPU, for outputting to the memory, a plurality of row address strobe signals corresponding to the eight DRAMs in a one-to-one relation, respectively. When one of the eight DRAMs is to be actually accessed, the CPU activates a corresponding byte enable signal, and the row address strobe control circuit selectively activates only one row address strobe signal corresponding to the activated byte enable signal.
REFERENCES:
patent: 5721862 (1998-02-01), Sartore et al.
patent: 5774409 (1998-06-01), Yamazaki et al.
Le Thong
NEC Corporation
Nelms David
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