Memory comprising simultaneously addressable memory elements

Details Memory comprising simultaneously addressable memory elements Memory comprising simultaneously addressable memory elements

1987-03-31

1989-07-04

Fears, Terrell W.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365 68, 365238, 365239, 36523809, G11C 800, G11C 502

Patent

active

048456780

ABSTRACT:
A random access memory (1) is described in which one address of a row of addresses is activatable. There is also realized a block addressing mode in which all addresses between a selectable first address and a selectable second address are activated. To this end there are provided two address registers (4, 5) and a logic tree structure (8) which consists of modules. At each level of the tree structure a module receives a part of the information from the two address registers in order to determine, possibly co-controlled by information received from a higher level of the tree, whether one or both limit addresses are situated within the address range covered by the module and, if the answer is negative, to determine whether all addresses of this address range must be activated or remain deactivated.

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patent: 4369504 (1983-01-01), Hanmura
patent: 4434502 (1984-02-01), Arakawa et al.
patent: 4725742 (1988-02-01), Tachimori et al.
patent: 4751684 (1988-06-01), Holt
"A Rectangular Area Filling Display System Architecture", by D. Whelan Computer Graphics, Jul. 1982, pp. 147-153, vol. 16, No. 3.
S. Demetrescu, "High Speed Rasterization Using a Highly Parallel Smart Bulk Memory", Technical Report No. 83-244, Computers Systems Laboratory,Stanford University (Jun. 1983).

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