Partially reconfigurable memory cell arrays

Partitioned decode circuit for low power operation

Pass gate decoder for a multiport memory dEvice that uses a sing

Pass gate with low transistor junction breakdown susceptibility

Path gate driver circuit

Phase change random access memory (PRAM) device

Power saving architecture for a cache memory

Power-gating system and method for integrated circuit devices

Precharge-enable self boosting word line driver for an embedded

Predecode column architecture and method

Predecode column architecture and method

Predecode column architecture and method

Predecoder control circuit

Presettable synchronous predecoded counter

Processor controlled command port architecture for flash memory

Programmable address decoder for field programmable memory array

Programmable address logic for solid state diode-based memory

Programmable impedance output buffer drivers, semiconductor devi

Programmable low voltage decode circuits with ultra-thin...

Programmable memory address decode array with vertical transisto