Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2008-05-27
2008-05-27
Elms, Richard T. (Department: 2824)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S194000, C365S185130
Reexamination Certificate
active
07379375
ABSTRACT:
Memory circuits having different configurations of local word line driving circuits (LWLDC) and methods for designing such circuits are provided. The memory circuits include an array of memory cells and a plurality of local word lines each coupled to a different subset of the array of memory cells. The memory circuit further includes a plurality of LWLDC respectively coupled to the plurality of local word lines, a global word line bus coupled to the plurality of LWLDC, and a global word line driving circuit (GWLDC) coupled to the global word line bus. At least one of the plurality of LWLDC may be configured to have a smaller amount of load capacitance than another LWLDC arranged comparatively farther from the GWLDC. In some embodiments, the variance of load capacitance may be induced by a variance of size among the plurality of LWLDC, specifically with reference to different transistor width dimensions.
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Cypress Semiconductor Corp.
Daffer Kevin L.
Daffer McDaniel LLP
Elms Richard T.
Wendler Eric
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