Memory cell decoder not including a charge pump

Details Memory cell decoder not including a charge pump Memory cell decoder not including a charge pump

2001-11-08

2003-05-06

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230030, C365S185110

Reexamination Certificate

active

06560162

ABSTRACT:

This application claims priority from Korean Patent Application No. 00-68729, filed Nov. 18, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile memory device and, more particularly, to a memory cell decoder not including a charge pump, a non-volatile semiconductor memory device including the memory cell decoder, and a method for supplying a high voltage to a memory cell array of the non-volatile semiconductor memory device.
2. Description of the Related Art
A non-volatile semiconductor memory device needs a voltage (for example, 20V) higher than a supply voltage Vcc supplied to read, write, or program data.
Non-volatile semiconductor memory devices include an array of memory cells. Each memory cell, in turn, comprises a memory cell transistor. In the memory cell transistor, a source and a drain are formed on both sides of a semiconductor substrate. A gate polysilicon is formed on the semiconductor substrate. A floating gate is formed on the gate polysilicon. A gate insulating film is stacked on the floating gate. A control gate is stacked on the gate insulating film.
When data is written into a cell or when a cell is programmed, ground (for example, 0V) is applied to the source, the drain, and the substrate. When a voltage higher than the supply voltage Vcc is applied to the control gate, electrons are implanted into the floating gate by Fowler-Nordheim tunneling, increasing a threshold level and thereby completing a write operation.
When data is erased, however, a high voltage is applied to the substrate and the ground is applied to the control gate, resulting in electrons being emitted from the floating gate to the substrate completing the erase operation.
Therefore, a high voltage must be applied to the control gate of the memory cell or the substrate to implant or emit electrons into the memory cell of the non-volatile semiconductor memory device.
The high control gate voltage must be able to be applied to the memory cell through a memory cell decoder that selects a memory cell.
FIG. 1
is a circuit diagram showing the memory cell decoder of a non-volatile semiconductor memory device. A row decoder for decoding the row address of the non-volatile semiconductor memory device includes a plurality of unit decoders (hereinafter, the memory cell decoders). The memory cell decoders include a string structure that is applied to an electrically erasable and programmable read-only memory (EEPROM) in the form of an AND operation.
Referring to
FIG. 1
, a memory cell decoder
10
includes a logic gate
1
, a transmission controller M
1
, a charge pump
7
, a word line enable signal line WLEN[
0
:n], and transmission transistors M
0
through Mn. The memory cell decoder
10
includes a transistor M
5
for driving a string select line SSL, a transistor M
4
for applying ground GND to the string select line SSL when a memory cell decoder is not selected, and a transistor M
8
for driving a ground select line GSL.
The logic gate
1
decodes an address Add for selecting a memory cell that is to be written, read, or programmed. When the memory cell is selected by the input address Add, the voltage at a node N
1
becomes the supply voltage Vcc. When the memory cell is not selected, the voltage of the node N
1
becomes GND (for example, 0V).
The transmission controller M
1
is formed of a depletion type NMOS transistor. The transmission controller M
1
controls the voltage of the node N
1
being transmitted to node N
2
responsive to a control clock nBLKSHF.
When the transistor M
2
and M
3
are turned on responsive to the voltage at node N
2
, the charge pump
7
transmits a high voltage signal Vpp higher than the supply voltage Vcc generated by a high voltage generator (not shown).
The word line enable signal WLEN[
0
:n] is an output signal of a word line driver (not shown). Also, the signal WLEN[
0
:n] is a voltage signal that swings higher than the supply voltage Vcc. The gates of the transmission transistors M
0
through Mn are turned on responsive to the signal at node N
2
boosted to a high voltage signal and transmits the signal WLEN[
0
:n] to the corresponding word line WL[
0
] through WL[n].
As the semiconductor memory devices become more integrated and the area of a unit memory cell is reduced, layout space for the memory cell decoder is likewise reduced.
The charge pump
7
includes a capacitor C for applying a high voltage signal VPP to the memory cell. The layout area utilized by the capacitor C is significantly larger, in turn, increasing the layout area of the charge pump
7
.
Also, as the operation source of the semiconductor memory device becomes smaller, the operation characteristics of the charge pump
7
deteriorates.
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome the disadvantages associated with prior art memory cell decoders and non-volatile semiconductor memory devices including memory cell decoders.
It is another object of the present invention to provide a method for reducing layout area of a memory cell decoder without deteriorating the operation characteristics even at a low supply voltage. A memory cell decoder using the method and a non-volatile semiconductor memory device including inventive the memory cell decoder are also provided.
To achieve the first object, there is provided a memory cell decoder including a first node and a first transmitting portion adapted to output a high voltage signal to the first node responsive to a first selection signal. A control portion is adapted to generate a first control signal responsive to an address and discharge the first node responsive to the first control signal. A second transmitting portion is adapted to output a word line enable signal responsive to the first selection signal and the first control signal.
The control portion includes the following: a first logic gate adapted to generate a first logic gate signal by logically manipulating the address; a second logic gate adapted to generate the first control signal by logically manipulating the first logic gate signal and a second control signal; an inverter for inverting the first control signal; and a discharge circuit adapted to discharge the first node responsive to the inverted first control signal.
The high voltage signal has a voltage higher than that of a supply voltage. The first selection signal is generated from a first pre decoder adapted to decode the address.
The first transmitting portion comprises a MOS transistor having a first and second stages and a gate, the first stage receiving the high voltage signal, the second stage being connected to the first node, and the gate receiving the first selection signal.
The first transmitting portion includes: a first MOS transistor having a first and second stages and a gate, the gate receiving the first selection signal and the second stage being connected to the first node; and a second MOS transistor having a first and second stages and a gate, the gate receiving a second selection signal, the first stage receiving the high voltage signal, and the second stage being connected to the first stage of the first MOS transistor.
The word line enable signal is generated by a second pre decoder adapted to decode the address. The word line enable signal has a voltage higher than that of a supply voltage.
The second transmitting portion includes a plurality of MOS transistors each having a first and second stages and a gate. The gate of each MOS transistor is connected to the first node. The second stage of each MOS transistor is connected to a corresponding word line. The first stage of each MOS transistor receives a corresponding word line enable signal. The memory cell decoder includes a clamping unit connected in parallel to the first transmitting portion and adapted to clamp a voltage at the first node. The clamping unit includes a MOS transistor having a first and second stages and a gate, the first stage and the gate being connected to the first node and the seco

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