Memory control system for controlling write-enable signals

Details Memory control system for controlling write-enable signals Memory control system for controlling write-enable signals

2001-01-09

2002-04-23

Tran, M. (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189020

Reexamination Certificate

active

06377510

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a high-speed memory access control system. More particularly, the present invention relates to the write-enable and data-mask control system of dynamic random access memory (DRAM) on a computer main board.
2. Description of Related Art
Most personal computer systems consist of a main board, interface cards and peripheral devices. The main computer board is the heart of a computer system. Besides having a central processing unit (CPU), a control chipset and a few slots for inserting interface cards, the main computer board also includes a plurality of memory slots. The number of memory modules inserted into the slots depends on the user's need. In general, each memory module consists of a few memory units. Nowadays, most personal computers have total internal memory ranging from a few tens of megabytes to several hundreds of megabytes.
The memory used inside most personal computers, such as synchronous dynamic access memory (SDRAM), transfers data in response to the rising edge of a clock pulse signal. However, there is another type of memory called double-data-rate dynamic random access memory (DDR DRAM). The DDR DRAM has double data transfer rate because the memory transfers data in response to both the rising edge and falling edge of a clock pulse signal.
At present, both SDRAM and DDR DRAM modules are developed in parallel. In general, DDR DRAM modules use memory slots that meet JEDEC standard 184-pin configuration while SDRAM modules use 168-pin memory slots. Due to considerations such as marketing, administration, production cost, compatibility and expandability, a main board that can support both SDRAM and DDR DRAM memory modules is in great demand. However, since 184-pin and 168-pin memory slots have slightly different designs for accommodating the operations of modules, the length of some signal lines on the main board may increase if both types of memory slots coexist.
Rapid development of semiconductor technologies has increased the processing power of CPU. Most personal computers now operate with a clocking frequency up to several hundred MHz. As the clocking rate of CPUs increase, the clocking frequency of memory units must also increase to 100 MHz or above. In high-speed operations, the layout of the control circuit for the memory modules must be designed such that long trace length is avoided. In addition, signal interference between conductive wires as well as timing factors must also be considered. Hence, to design a motherboard having slots capable of accommodating both 184-pin and 168-pin memory modules is a difficult task.
FIG. 1
is a diagram showing a conventional write-enable control system of a computer main board having both 184-pin and 168-pin memory slots thereon. As shown in
FIG. 1
, a control chipset
10
having just one write-enable pin SWE#, a 184-pin memory slot
12
and a 168-pin memory slot is provided. The 184-pin memory slots
12
has one write-enable pin WE#, but the 168-pin memory slot
14
has two write-enable pins WE
1
# and WE
2
#, the 27
th
and 48
th
pin respectively. The overall length L of write-enable line includes the distance L
1
from the write-enable pin SWE# of the control chipset
10
to the write-enable pin WE# of the 184-pin memory slot
12
, the distance L
2
from the write-enable pin WE# of the memory slot
12
to the first write-enable pin WE
1
# of the 168-pin memory slot
14
and the distance L
3
from the write-enable pin WE
1
# of the 168-pin memory slot
14
to the write-enable pin WE
2
# of the same memory slot
14
.
In a typical example, the overall length L i.e. L
1
+L
2
+L
3
) is about 4877 mils. In general, a shorter trace length can have a larger timing margin. For a trace length of up to 4877, the timing margin is rather small which may pin to system instability. Moreover, the long trace line renders rapid one-cycle (1T) memory access command difficult to implement. However, a memory access command timing of two cycles (2T) can reduce the operating speed of a system considerably. This is extremely important for a computer system having DDR DRAM modules.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a memory control system that enables system designers to design a computer system having slots that can accommodate two different types of memory modules. Moreover, the computer system is able to maintain a high timing margin even when operating at a high operating speed so that system stability is improved. Furthermore, because the system permits the incorporation of one cycle (1T) timing into the design of memory access commands, system performance of the computer system is boosted.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a memory control system for controlling write-enable signals. The memory control system includes a first memory slot, a second memory slot and control chipset. The first memory slot has a write-enable pin thereon, and the slot can accommodate a first type of memory module. The second memory module has a first write-enable pin and a second write-enable pin thereon, and the slot can accommodate a second type of memory module. The control chipset has a write-enable pin and a dual-purpose write-enable/memory-parity-data pin. The chipset controls data transaction with any first type memory module in the first memory slot and any second type memory module in the second memory slot. The write-enable pin of the control chipset is connected to the write-enable pin of the first memory slot and the first write-enable pin of the second memory slot. The write-enable/memory-parity-data pin of the chipset is connected to the second write-enable pin of the second memory slot.
With regard to the memory control system of this invention, an enable signal is sent from the write-enable/memory-parity-data pin when the control chipset writes data into the second memory module. The first memory slot of this invention can include a memory-parity-data pin. The memory-parity-data pin of the first memory slot and the write-enable/memory-parity-data pin of the control chip can be connected together. Whenever the control chipset writes data into the first type memory module with the first type memory module having parity-data memory, the write-enable/memory-parity-data pin will assert a memory-parity-data signal.
According to the memory control system of this invention, the control chipset includes a multiplexer. The multiplexer is controlled by selection signals such that output from the multiplexer is equivalent to the write-enable signal or the memory-parity-data signal. As soon as the computer system of this embodiment is switched on, the computer system will attempt to read the grouping signal of the second type memory module plugged into the second memory slot. Hence, the selection signals of the multiplexer are set and consequently a write-enable signal or a memory-parity-data signal is asserted from the write-enable/memory-parity-data pin. A computer system similar to the type illustrated in this invention can further include a basic input/output system (BIOS). Hence, the user is able to set the group information via the BIOS so that the selection signals of the multiplexer are also set.
This invention also provides a memory control method suitable for controlling memory write-enable signals in a computer system. The computer system includes a first memory slot having a write-enable pin thereon for plugging a first type memory module, a second memory slot having a first write-enable pin and a second write-enable pin thereon for plugging a second type memory module and a control chipset. The method includes the following steps. First, a write-enable pin and a dual-purpose write-enable/memory-parity-data pin are provided on the control chipset. The write-enable pin of the control chipset is connected to the write-enable pin of

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