Read/write memory with plural memory cell write capability at a

Details Read/write memory with plural memory cell write capability at a Read/write memory with plural memory cell write capability at a

1994-08-16

1996-06-18

Lane, Jack A.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518902, 36523003, 365220, 365221, G11C 700

Patent

active

055285511

ABSTRACT:
A read/write memory for use with a central processing unit is disclosed, which has the capability of writing the same data state to multiple memory cells in a selected row in a single cycle. The invention is incorporated into the memory by a capacitor which is selectively connected to one of the bit lines received by each sense amplifier to override the sensing operation, thereby setting the polarity of the sensed differential voltage to a predetermined state. The restoring operation of the sense amplifier restores the sensed data state into the selected memory cell, completing the write. In response to a control signal generated in the read/write memory, the capacitor is connectable to multiple bit lines, for efficiency of design. Each capacitor has sufficient capacitance to fully discharge a stored "1" value plus the dummy capacitor charge, for each of the bit lines to which it will be connected. Logic is incorporated into the memory to receive the data state to be written, and to receive the least significant bit of the row address. The logic connects the capacitor to the bit line to which the storage cell is connected in order to write a "0" state (the capacitor being precharged to ground), and connects the capacitor to the bit line to which the dummy cell is connected in order to write a "1" state. For a multiple input/output memory, a write mask may be included to inhibit the writing by the capacitor for selected arrays of the memory. A data input register may also be provided for storing the data to be written for multiple write cycles.

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