Reduced line select decoder for a memory array

Details Reduced line select decoder for a memory array Reduced line select decoder for a memory array

2000-05-01

2001-06-26

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S190000

Reexamination Certificate

active

06252819

ABSTRACT:

FIELD OF INVENTION
This invention relates to semiconductor memory devices and particularly to a line select decoder for a memory array.
BACKGROUND OF INVENTION
FIG. 1
schematically shows a typical circuit of a 2-to-1 line decoder for a dynamic semiconductor memory device in the prior art. P-channel MOS transistors P
1
204
and P
3
206
together with N-channel MOS transistors N
1
208
and N
3
210
are transfer devices that connect a bit line pair BIT
200
and /BIT
201
to a sense amplifier and write circuit blocks. P-channel MOS transistors P
2
205
and P
4
207
and N-channel MOS transistors N
2
209
and N
4
211
likewise connect BIT
2
202
and /BIT
2
203
to the same ports of the sense amplifier and write blocks. To selectively transfer the column bit line pairs BIT
200
and /BIT
201
or BIT
2
202
and /BIT
2
203
to the sense amplifier for either a read or write operation, it is necessary to activate four separate control lines for reading and writing, namely, WY
0
216
, WY
1
217
, RY
0
214
and RY
1
215
. In the interest of conserving chip real estate and performance it is as usual always desirable to provide a simplified bit line decoder with improved efficiency for either a read or a write operation.
SUMMARY OF INVENTION
An object of the invention is to minimize the amount of line select control signals needed to transfer data between a memory array and a sense amplifier or a write buffer.
Another object of the invention is to achieve a fast transfer of data between a memory array and a sense amplifier or a write buffer. In accordance with the principles of this invention, a semiconductor memory device is provided comprising a pair of bit line select control signals to select a bit line from an array of memory cells for a read/write operation on the selected bit line. In the preferred embodiment, both the true and complementary signal associated with the selected bit line are selected. A sense amplifier is coupled to the selected bit line via a P-type transistor for differentially amplifying the voltages on the selected bit line in accordance with the voltage on the sense drive line. The sense amplifier is coupled to receive a sense amplifier control input responsive to activation of a sense instructing signal during a read operation to latch data into the sense amplifier. A write buffer is also coupled to the selected bit line via an N-type transistor, responsive to a write control signal to write to the selected bit line during a write operation.


REFERENCES:
patent: 4916668 (1990-04-01), Matsui
patent: 4954992 (1990-09-01), Kumanoya et al.
patent: 5010521 (1991-04-01), Matsui
patent: 5367492 (1994-11-01), Kawamoto et al.
patent: 5381367 (1995-01-01), Kajimoto
patent: 5497352 (1996-03-01), Magome
patent: 5675548 (1997-10-01), Yokoyama
patent: 5896342 (1999-04-01), Nakao
patent: 5963500 (1999-10-01), Taura et al.
patent: 6067264 (2000-05-01), Kwon

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