Reduced leakage driver circuit and memory device employing same

Details Reduced leakage driver circuit and memory device employing same Reduced leakage driver circuit and memory device employing same

2007-11-29

2009-12-15

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230080, C365S233110, C365S233100

Reexamination Certificate

active

07633830

ABSTRACT:
A row line driver circuit for use in a memory array including multiple memory cells and multiple row lines coupled to the memory cells for selectively accessing the memory cells includes an output stage adapted for connection to a corresponding one of the row lines and a control circuit connected to the output stage. The output stage is operative during an active phase of a given memory cycle to drive the corresponding row line to a potential as a function of at least one address signal received by the driver circuit. The control circuit is operative to generate at least one control signal for disabling the output stage at least during an inactive phase of the memory cycle to thereby substantially eliminate a leakage current path in the driver circuit.

REFERENCES:
patent: 2007/0263470 (2007-11-01), Derner et al.

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