Reduced area word line driving circuit for random access memory

Details Reduced area word line driving circuit for random access memory Reduced area word line driving circuit for random access memory

1995-09-26

1997-05-27

Popek, Joseph A.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518911, G11C 700

Patent

active

056338325

ABSTRACT:
A word line driver circuit (10) for driving four word lines (18) is disclosed. In a preferred embodiment, the word line driver circuit (10) includes a decoder circuit (12) for pulling a decode node (20) to a logic low level (Vss) in response to internal row decode signals, a pull-up circuit (14) for pulling the decode node (20) to a logic high (Vcc) to deselect the word lines (18), four transfer transistors (NO) intermediate the decode node (20) and four control nodes (22), four CMOS inverters (18), each driving one word line (18) between a boost voltage and Vss. A PMOS level shifter transistor (P0) is associated with each inverter (18), and has a channel width that is small relative to both the channel widths of the transfer transistors (N0) and to the devices making up the decoder circuit (12), allowing the level shifter transistors (P0) to be overpowered by the decoder circuit (12). The channel width of the inverter NMOS transistors (N2) are relatively large in relation to the inverter PMOS transistors (P2), allowing the NMOS transistors (N2) to be turned on by a voltage of Vcc-Vtn, where Vtn is the threshold voltage of the transfer transistors (N0).

REFERENCES:
patent: 4649521 (1987-03-01), Tsuchida et al.
patent: 4951259 (1990-08-01), Sato et al.
patent: 5282171 (1994-01-01), Tokami et al.
patent: 5363338 (1994-11-01), Oh
patent: 5412331 (1995-05-01), Jun et al.

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