Redundancy semiconductor memory device which utilizes spare memo

Details Redundancy semiconductor memory device which utilizes spare memo Redundancy semiconductor memory device which utilizes spare memo

1993-02-04

1995-12-12

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365200, 36523003, 371 103, G11C 700

Patent

active

054756480

ABSTRACT:
A semiconductor memory device with a redundancy configuration with a higher corrective efficiency is disclosed. Primary memory cell arrays 3a, 3b, and 3c are arranged in memory cell blocks a, b, and c. spare memory cell arrays 2b and 2c are arranged in the memory cell blocks b and c. When the address of an address signal supplied agrees with the address of a defective primary memory cell in one memory cell block, a spare memory cell in the other memory cell block selected for such a defective memory cell. Even if a word line of the primary and a word line of the spare memory cells are selected at the same time, it is possible to access read data in a nondestructive manner. This achieves a high-speed word line activation as well as an improved corrective efficiency. The provision of a row decoder that connects a primary word line to a spare word line with a shared decode line prevents the increase of the area of memory chips due to the arrangement of a Spare memory cell.

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