Redundant semiconductor memory device using a single now address

Details Redundant semiconductor memory device using a single now address Redundant semiconductor memory device using a single now address

1996-12-03

1998-12-08

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365200, 36518908, 36523008, 36523003, 3652257, G11C 800

Patent

active

058480064

ABSTRACT:
A drive circuit for a semiconductor memory device in which a plurality of memory cell arrays are driven by a divisional decode system, includes a single, row address decoder including a plurality of address latch circuits for holding an address signal for normal operation via a first logic gate unit, and a plurality of normal/redundancy switching circuits for inputting therein held data, and an address signal for redundancy purposes, and for switching the input signal in response to a judging signal for redundancy purposes. The outputs of the switching circuits are activated through a second logic gate unit into which a row address enable signal is inputted. Thus, a driver selection signal during normal operation and a driver selection signal during a redundancy operation are commonly used. As a result, a total number of wiring lines and the number of driver circuits, as well as the chip area, are reduced.

REFERENCES:
patent: 5581508 (1996-12-01), Sasaki et al.
patent: 5596542 (1997-01-01), Sugibayashi et al.

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