Reduced delay address decoders and decoding methods for...

Details Reduced delay address decoders and decoding methods for... Reduced delay address decoders and decoding methods for...

1998-11-03

2001-01-30

Mai, Son (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230080

Reexamination Certificate

active

06181635

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuit memory devices, and more particularly to address decoders and decoding methods for integrated circuit memory devices.
BACKGROUND OF THE INVENTION
Integrated circuit memory devices are widely used in consumer and commercial electronics. It is generally desirable to increase the speed of integrated circuit memory devices. Speed may be increased by reducing the delays in read and write operations of the memory devices. For example, the delay in activating a word line in response to address signals may be reduced. This delay may be caused by standby time that is used to activate components after a control signal is applied, transmission delays at each buffer or gate, and precharging times.
FIG. 1
is a block diagram of a conventional row address decoder. The delays that are produced in the row address decoder will be described with reference to FIG.
1
.
In
FIG. 1
, address buffers
10
a
and
10
b
receive external input signals Ai and Aj of a TTL level and convert the level of the received signals to a CMOS level, to thereby generate the converted signals as address signals PAi and PAj. A row address latch
12
receives the address signals PAi and PAj and latches the received address signals in accordance with an internal clock PCLK and an activation command PRA to generate the latched address signals as effective addresses RAij. A predecoder
14
predecodes the effective addresses RAij and generates predecoded addresses DRAij. A main decoder
16
, which may be present for each bank in the memory device, receives the predecoded addresses DRAij, and main-decodes and sufficiently boosts such signal to drive a word line at the boosted voltages WLij.
FIG. 2
is a timing diagram showing a timing relationship of signals of
FIG. 1
during operation of the address decoder.
When a row active command ACTIVE is asserted, the level of the external signals Ai and Aj is shifted to a CMOS level by the address buffers
10
a
and
10
b
, and then latched in response to the internal clock PCLK and the activation command PRA. After the latched address signals are output as the effective addresses RAij, the predecoder
14
is enabled in response to an enable signal PDRAE to generate the predecoded addresses DRAij. When a precharge command PRECHARGE is asserted, the decoded addresses DRAij is reset by a predecoder reset signal PDRAP and the decoder returns to a precharge state.
As shown in
FIG. 2
, even after the decoded addresses DRAij are output, the effective addresses RAij maintains the previous state until a next activation command PRA is input. Accordingly, the predecoder
14
should not be enabled until new effective addresses RAij are generated since the previous effective addresses RAij are applied to the predecoder
14
until the new effective addresses RAij are generated. If the predecoder
14
is enabled before the new effective addresses RAij are generated, the new effective addresses RAij may not be applied to the predecoder
14
, so that a wrong word line may be selected.
As described above, since the predecoder
14
should not be enabled until the new effective addresses RAij are generated, there should be a sufficient standby time before the predecoder enable signal PDRAE is asserted to enable the predecoder after the effective addresses RAij are generated. This may be an obstacle in increasing the speed of the memory device.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved address decoders and decoding methods for integrated circuit memory devices.
It is another object of the invention to provide address decoders and decoding methods that can reduce the time for enabling the address decoder after an external address is provided.
These and other objects are provided, according to the present invention, by enabling the predecoder before the effective address is generated by the address latch. Accordingly, the predecoder can operate as soon as the effective address is generated by the address latch. The effective address is also preferably reset after the predecoded address is generated from the effective address. The effective address may be reset by disabling the predecoder after the predecoded address is generated from the effective address and resetting the effective address after the predecoder is disabled. Thus, the standby time before the predecoder is enabled after the effective address is generated may be reduced and preferably minimized. Operational speed of the integrated circuit memory device can therefore be increased.
Address decoders according to the invention receive an address signal and decode the address signal to drive word lines of an integrated circuit memory device. The address decoder includes an address latch that generates an effective address from the address signal. A predecoder generates a predecoded address from the effective address. A main decoder generates from the predetermined address a main address that is applied to the word lines. A first circuit enables the predecoder before the effective address is generated by the address latch. A second circuit may also be provided that resets the effective address after the predecoded address is generated from the effective address. The second circuit may include a circuit that disables the predecoder after the predecoded address is generated from the effective address and a circuit that resets the effective address after the predecoder is disabled.
In another embodiment of address decoders according to the invention, an address latch predecoder latches the address signal and generates a predecoded effective address from the latched address signal. A bank enable circuit latches the predecoded effective address to provide a predecoded address. A main decoder generates from the predecoded address a main address that is applied to the word lines. A first circuit enables the bank enable circuit before the effective address is generated by the address latch predecoder. A second circuit may reset the predecoder effective address after the predecoded address is generated from the predecoded effective address. The second circuit may include a circuit that disables the address latch predecoder after the predecoded address is generated from the predecoded effective address and a circuit that resets the predecoded effective address after the address latch predecoder is disabled. Accordingly, reduced delay address decoders and decoding methods may be provided.


REFERENCES:
patent: 4731761 (1988-03-01), Kobayashi
patent: 5748557 (1998-05-01), Kang
patent: 5844857 (1998-12-01), Son et al.
patent: 5852585 (1998-12-01), Koshizuka

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