Redundancy decoding circuit having automatic deselection

Details Redundancy decoding circuit having automatic deselection Redundancy decoding circuit having automatic deselection

1999-08-02

2000-10-17

Le, Vu A.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365194, 365200, G11C 700

Patent

active

061341770

ABSTRACT:
A redundancy decoding circuit reduces standby power consumption in a memory device by automatically deactivating a deselect signal after a burst read/write operation, thereby eliminating a current path through the redundancy decoding circuit. The redundancy decoding circuit includes a pulse generator which generates a pulse signal having a predetermined pulse width that is just long enough to accommodate a read/write operation. The pulse signal is applied as the deselect signal to a drive circuit which provides drive current to a comparator for decoding a redundant address. A pulse begins when the chip select signal is activated and ends after a predetermined time. The pulse generator is implemented as plurality of series-connected flip-flops and a logic circuit for combining the outputs from the flip-flops which are clocked by a common clock signal.

REFERENCES:
patent: 5146429 (1992-09-01), Kawai et al.
patent: 5471426 (1995-11-01), McClure
Samsung Electronics Document, "64K.times.36 Synchronous SRAM", May 1999, pp. 1-15.

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