Reversible polarity decoder circuit

Details Reversible polarity decoder circuit Reversible polarity decoder circuit

2006-12-31

2009-06-02

Lam, David (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S185230, C365S189090

Reexamination Certificate

active

07542370

ABSTRACT:
A reversible polarity decoder circuit is disclosed which is particularly suitable for implementing a multi-headed decoder structure, such as might be used for decoding word lines, and particularly in a 3D memory array. The decoder circuit provides an overdrive voltage bias to the gates of half-selected word line driver circuits to solidly maintain the half-selected word lines at an inactive level. If the memory array is biased at or near the breakdown voltage, this overdrive voltage may be greater than the breakdown voltage of the decoder transistors. However, in the embodiments described, the decoder circuit accomplishes this without impressing a voltage greater than the breakdown voltage across any of the decoder transistors, for either polarity of operation of the decoder circuit.

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