Redundancy decoding circuit using n-channel transistors

Details Redundancy decoding circuit using n-channel transistors Redundancy decoding circuit using n-channel transistors

1989-02-10

1992-02-11

Popek, Joseph A.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365 49, 365200, G11C 800

Patent

active

050880667

ABSTRACT:
Four n-channel transistor, single-stage XNOR/XOR decoding circuit provides for an improved performance of a decoding circuit using CAMs to access redundant memory.

REFERENCES:
patent: 3633175 (1972-01-01), Harper
patent: 3659275 (1972-04-01), Marshall
patent: 3735368 (1973-05-01), Beausoleil
patent: 3753235 (1973-08-01), Daughton et al.
patent: 3753244 (1973-08-01), Sumilas et al.
patent: 4051354 (1977-09-01), Choate
patent: 4250570 (1981-02-01), Tsang et al.
patent: 4358833 (1982-11-01), Folmsbee et al.
patent: 4441170 (1984-04-01), Folmsbee et al.
patent: 4862417 (1989-08-01), List et al.
G. Canepa et al., "A 90ns 4Mb CMOS EPROM", ISSCC 88, Session X, Feb. 18, 1988, pp. 120-125.

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