Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2000-04-19
2002-08-20
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S189011, C365S200000
Reexamination Certificate
active
06438065
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application relates to
1. U.S. patent application Ser. No. 09/553,571 entitled:
“Non-Volatile Memory Array Using Gate Breakdown Structures” commonly owned and filled concurrently with the present application.
2. U.S. patent application Ser. No. 09/552,625 now U.S. Pat. No.: 6,243,294 B1 entitled: “Improved Array Arrangement for Non-Volatile Memory Using Gate Breakdown Structure in Stantard Sub 0.25 Micron CMOS Process” commonly owned and filed concurrently with the present application.
1. Technical Field
This invention relates to integrated circuits, particularly programmable logic devices of field programmable gate arrays (FPGAs). More particularly, this invention relates to a redundancy system for storing a decryption key that reduces the possibility that the decryption key is read improperly.
2. Background of the Invention
Field programmable gate arrays (FPGAs) are configured to perform particular functions by loading a stream of bits, or bitstream, into the FPGA. Each time an FPGA is powered-up or reset, the bitstream containing the FPGA functions is re-loaded into the FPGA.
Since the bitstream describes the functions performed by the FPGA, an individual may monitor or otherwise capture of copy of the bitstream in an effort to copy the functionality of the FPGA. To discourage this type of copying activity, the bitstream is encoded prior to transmitting the bitstream to the FPGA. For example, the bitstream can be encoded by an encoder using an encryption key. To properly utilize the encoded bitstream, the FPGA must first decode the bitstream. For example, a decoder in the FPGA uses a decryption key to decode the bitstream. Once decoded, the bitstream is used by the remianing portions of the FPGA to define the functions performed by the FPGA.
To adequately protect the content of the bitstream, the user should be able to program the encryption key and the decryption key after the FPGA is manufactured. Thus, different FPGAs may use different pairs of keys (i.e., encryption key and decryption key) to encode the bitstream. Typical FPGAs include a non-volatile memory for storing decryption keys, adjusting (or “trimming”) internal parameters, and other data that should be maintained when the FPGA is powered-down or reset. This non-volatile memory is programmed to store the decryption key. Each time the FPGA is powered-up or reset, the encoded bitstream is received and decoded by a decoder using the decryption key stored in non-volatile memory.
However, if one or more bits of the decryption key are corrupted or cannot be read accurately from the non-volatile memory, then the encoded bitstream cannot be properly decoded. The FPGA will not operate properly unless the bitstream is decoded accurately. Therefore, it is desirable to provide a system to avoid improperly reading the decryption key from the non-volatile memory.
SUMMARY OF THE INVENTION
The present invention provides a redundant non-volatile memory array that stores data (such as a decryption key) in a manner that reduces the possibility of misreading the stored data from the redundant non-volatile memory array. One aspect of the invention provides a first non-volatile memory cell and a second non-volatile memory cell, each of which is capable of storing at least one bit of information. The second non-volatile memory cell provides redundant storage of the information stored in the first non-volatile memory cell. A read circuit coupled to the first and second non-volatile memory cells reads the information stored in the first and second non-volatile memory cells.
According to another implementation, the read circuit simultaneously reads the information stored in the first and second non-volatile memory cells. Additionally, the read circuit is able to read information stored in the first non-volatile memory if the second non-volatile memory is defective or is not programmed properly.
In a described embodiment of the invention, each non-volatile memory cell includes a storage transistor having a source and a drain, both of which are coupled to ground.
Another aspect of the invention provides an access transistor coupled to a storage transistor. In this embodiment, the storage transistor is programmed through the access transistor. Additionally, each storage transistor has a gate oxide. Each non-volatile memory cell is programmed by breaking the gate oxide of the storage transistor.
Another aspect of this invention provides a first decoder coupled to the first non-volatile memory cell and a second decoder coupled to the second non-volatile memory cell. The first and second decoders select the first or second non-volatile memory cell for programming.
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Hart Michael J.
Rao Kameswara K.
Voogel Martin L.
Brown Scott R.
Ho Hoai V.
Le Thong
Xilinx , Inc.
Young Edel M.
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