RAM variable size block write

Details RAM variable size block write RAM variable size block write

1994-04-11

1996-08-13

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518904, G11C 700, G11C 800

Patent

active

055463509

ABSTRACT:
A method of enabling a controllable and variable number of bits to be written to a group of cells of a DRAM or SRAM simultaneously in a block, wherein a predecoded column address signal is decoded for enabling writing to cells of the DRAM or SRAM, and the predecoded column address signal is block overwritten by means of a block address signal, whereby plural decoders are enabled simultaneously for simultaneous writing to a column of cells notwithstanding the logic levels of the predecoded address signal.

REFERENCES:
patent: 5311479 (1994-05-01), Harada
patent: 5329492 (1994-07-01), Mochizuki

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