LandOfFree - US Patents - Listing for Semiconductor device manufacturing: process,Making field effect device having pair of active regions...

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Structure and method for dual gate oxide thicknesses

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Structure and method for dual gate oxide thicknesses

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Structure and method for dual work function logic devices in...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Structure and method for dual-gate FET with SOI substrate

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate

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Structure and method for fabricating self-aligned metal...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Structure and method for forming asymmetrical overlap...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Structure and method for forming asymmetrical overlap...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Structure and method for forming the gate electrode in a...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

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Structure and method for gated lateral bipolar transistors

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Structure and method for gated lateral bipolar transistors

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Structure and method for improved latch-up using dual depth...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Structure and method for improved memory arrays and improved ele

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Structure and method for improved stress and yield in pFETS...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Structure and method for integrating MIM capacitor in BEOL...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Structure and method for latchup improvement using through...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Structure and method for making a notched transistor with...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate

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Structure and method for manufacturing asymmetric devices

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Structure and method for manufacturing MOSFET with...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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Structure and method for manufacturing planar SOI substrate...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

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Structure and method for manufacturing planar strained...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

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