Structure and method for integrating MIM capacitor in BEOL...

Details Structure and method for integrating MIM capacitor in BEOL... Structure and method for integrating MIM capacitor in BEOL...

2007-01-09

2007-01-09

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S439000, C438S329000, C438S393000, C438S396000, C257SE21009, C257SE21011

Reexamination Certificate

active

10906521

ABSTRACT:
A method for integrating a metal-insulator-metal (MIM) capacitor in back end of line (BEOL) wiring levels of a semiconductor device includes forming an isolating layer over a lower wiring level, forming a bottom electrode of the capacitor on the isolating layer, and forming an interlevel dielectric material on the isolating layer and the bottom electrode. A capacitor dielectric is formed on the bottom electrode and a top electrode of the capacitor is formed on the capacitor dielectric, wherein the top electrode is formed concurrently with an upper wiring level, the upper level being the next successive wiring level with respect to the lower wiring level.

REFERENCES:
patent: 6624040 (2003-09-01), Ng et al.
patent: 6670237 (2003-12-01), Loh et al.
patent: 6825075 (2004-11-01), Petrarca et al.
patent: 2002/0197815 (2002-12-01), Yoshitomi
patent: 2003/0025143 (2003-02-01), Lin et al.
patent: 2004/0104420 (2004-06-01), Coolbaugh et al.
patent: 2004/0251514 (2004-12-01), Abadeer et al.

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