Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-07-19
2011-07-19
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S294000, C438S592000
Reexamination Certificate
active
07981751
ABSTRACT:
A semiconductor structure including at least one transistor is provided which has a stressed channel region that is a result of having a stressed layer present atop a gate conductor that includes a stack comprising a bottom polysilicon (polySi) layer and a top metal semiconductor alloy (i.e., metal silicide) layer. The stressed layer is self-aligned to the gate conductor. The inventive structure also has a reduced external parasitic S/D resistance as a result of having a metallic contact located atop source/drain regions that include a surface region comprised of a metal semiconductor alloy. The metallic contact is self-aligned to the gate conductor.
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Pan, J., et al., “Novel approach to Reduce Source/drain Series Resistance in High Performance CMOS Devices Using Self-Aligned CoWP Process for 45 nm Node UTSOI Transistors with 20 nm Gate Lengths”, VLSI 2006.
Pan, J. et al. “Novel approach to Reduce Source/drain Series Resistance in High Performance CMOS Devices Using Self-Aligned CoWP Process for 45 nm Node UTSOI Transistors with 20 nm Gate Lengths”, VLSI 2006.
Rausch Werner
Zhu Huilong
Abate Esq. Joseph P.
International Business Machines - Corporation
Pham Long
Scully , Scott, Murphy & Presser, P.C.
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