Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
2007-09-04
2007-09-04
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
Reexamination Certificate
active
11265464
ABSTRACT:
A method of forming a dual gate fin-type field effect transistor (FinFET) structure patterns silicon fins over an insulator and patterns a gate conductor at an angle to the fins. The gate conductor is formed laterally adjacent to and over center portions of the fins. The gate conductor is planarized such that the gate conductor is separated into distinct gate conductor portions that are separated by the fins. These gate conductor portions include front gates and back gates. The front gates and the back gates alternate along the structure, such that each fin has a front gate on one side and a back gate on the opposite side. Then front gate wiring is formed to the front gates and back gate wiring is formed to the back gates.
REFERENCES:
patent: 6413802 (2002-07-01), Hu et al.
patent: 7-321297 (1995-12-01), None
patent: 2000-68517 (2000-03-01), None
patent: 2001-257358 (2001-09-01), None
patent: 2003-17710 (2003-01-01), None
patent: 5-48104 (2003-02-01), None
Nowak Edward J.
Williams Richard Q.
Coleman W. David
Gibb & Rahman, LLC
International Business Machines - Corporation
Sabo, Esq. William D.
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