LandOfFree - US Patents - Listing for Semiconductor device manufacturing: process,Making field effect device having pair of active regions...,Having junction gate

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Active photosensitive structure with buried depletion layer

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate

Reexamination Certificate

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Advanced JFET with reliable channel control and method of...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate

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Apparatus and manufacturing process of carbon nanotube gate...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate

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Asymmetric depletion region for normally off JFET

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate

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Bipolar transistor with collector having an epitaxial Si:C...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate

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Capacitor plate formation in a mixed analog-nonvolatile...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate

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Capping layer

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate

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Carbon nanotube gate field effect transistor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate

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Deep buried channel junction field effect transistor (DBCJFET)

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate

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Deep buried channel junction field effect transistor (DBCJFET)

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate

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Distributed high voltage JFET

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate

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Double gate trench transistor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate

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Double LDD devices for improved dram refresh

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate

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Double LDD devices for improved DRAM refresh

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate

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Dual double gate transistor and method for forming

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate

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Edge structure for relaxing electric field of semiconductor...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate

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Fabrication of multiple field-effect transistor structure having

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate

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Fin-JFET

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate

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Formation of planar strained layers

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate

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Gate self aligned low noise JFET

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate

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