Gate self aligned low noise JFET

Details Gate self aligned low noise JFET Gate self aligned low noise JFET

2007-03-08

2010-06-29

Bryant, Kiesha R (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having junction gate

C438S186000, C438S196000, C438S526000, C438S595000, C257SE21445, C257SE21446

Reexamination Certificate

active

07745274

ABSTRACT:
The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.

REFERENCES:
patent: 4214215 (1980-07-01), Mellen et al.
patent: 5012305 (1991-04-01), Khadder et al.
patent: 5120669 (1992-06-01), Schrantz
patent: 5192699 (1993-03-01), Bulat et al.
patent: 5498885 (1996-03-01), Deen et al.
patent: 5786615 (1998-07-01), Saito
patent: 6790736 (2004-09-01), Wu
patent: 7648898 (2010-01-01), Banna
patent: 2002/0175383 (2002-11-01), Kocon et al.
patent: 2005/0067631 (2005-03-01), Pendharker et al.
patent: 2008/0014687 (2008-01-01), Vora et al.
patent: 2008/0093635 (2008-04-01), Kobayashi
patent: 2008/0272402 (2008-11-01), Saha et al.

Affiliated with

Also associated with

Rating

Gate self aligned low noise JFET does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Gate self aligned low noise JFET, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gate self aligned low noise JFET will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4240407