Formation of planar strained layers

Details Formation of planar strained layers Formation of planar strained layers

2002-08-02

2004-05-04

Thompson, Craig A. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having junction gate

Reexamination Certificate

active

06730551

ABSTRACT:

FILED OF THE INVENTION
This invention relates generally to semiconductor substrates and particularly to semiconductor substrates with strained layers.
BACKGROUND
The recent development of silicon (Si) substrates with strained layers has increased the options available for design and fabrication of field-effect transistors (FETs). Enhanced performance of n-type metal-oxide-semiconductor (NMOS) transistors has been demonstrated with heterojunction metal-oxide-semiconductor field effect transistors (MOSFETs) built on substrates having strained silicon and relaxed silicon-germanium (SiGe) layers. Tensilely strained silicon significantly enhances electron mobilities. NMOS devices with strained silicon surface channels, therefore, exhibit improved performance with higher switching speeds. Hole mobilities are enhanced in tensilely strained silicon as well, but to a lesser extent for strain levels less than approximately 1.5%. Accordingly, equivalent enhancement of p-type metal-oxide-semiconductor (PMOS) device performance in such surface-channel devices presents a challenge.
Hole mobility enhancement has been demonstrated in highly strained SiGe layers. The formation of such highly strained layers is made difficult by the tendency of these layers to undulate, especially with increasing strain levels, i.e., with high Ge content. This undulation lowers hole mobilities, thereby offsetting the beneficial mobility enhancement provided by the strained layers.
The observed undulation arises from lattice mismatch with respect to an underlying layer, and increases in severity with formation temperature. Unfortunately, the formation of a tensilely strained layer made of, for example, Si, over the compressively strained layer is desirably carried out at a relatively high temperature, e.g., 550° C., to achieve a commercially viable formation rate and uniformity.
SUMMARY
The present invention facilitates formation of the tensilely strained layer at a relatively high average temperature, while keeping the compressively strained layer substantially planar. In accordance with the invention, the tensilely strained layer is initially grown at a relatively low temperature (i.e., sufficiently low to avoid undulations in the compressively strained layer) until a thin layer of the tensilely strained layer has been formed. It is found that this thin layer suppresses undulation in the compressively strained layer even at higher process temperatures that would ordinarily induce such undulation. As a result, formation of the tensilely strained layer may continue at these higher temperatures without sacrificing planarity.
In one aspect, therefore, the invention features a method for forming a structure based on forming a compressively strained semiconductor layer having a strain greater than or equal to 0.25%. A tensilely strained semiconductor layer is formed over the compressively strained layer. The compressively strained layer is substantially planar, having a surface roughness characterized by at least one of (i) an average roughness wavelength greater than an average wavelength of a carrier in the compressively strained layer and (ii) an average roughness height less than 10 nm.
One or more of the following features may also be included. The compressively strained layer may include at least one group IV element, such as at least one of silicon and germanium. The compressively strained layer may include >1% germanium. The tensilely strained layer may include silicon. The compressively strained layer may include at least one of a group III and a group V element. The compressively strained layer may include indium gallium arsenide, indium gallium phosphide, and/or gallium arsenide. The compressively strained layer may include at least one of a group II and a group VI element. The compressively strained layer may include zinc selenide, sulphur, cadmium telluride, and/or mercury telluride. The compressively strained layer may have a thickness of less than 500 Å, including less than 200 Å.
The compressively strained layer may be formed at a first temperature, and at least a portion of the tensilely strained layer may be formed at a second temperature, with the second temperature being greater than the first temperature. The tensilely strained layer may include silicon and the second temperature may be greater than 450° C. A first portion of the tensilely strained layer may be formed at a first temperature and a second portion of the tensilely strained layer may be formed at the second temperature, the first temperature being sufficiently low to substantially avoid disruption of planarity, with the first portion of the tensilely strained layer maintaining the planarity of the compressively strained layer notwithstanding transition to the second temperature.
The tensilely strained layer may be formed at a rate greater than 100 Å/hour. The compressively strained layer and/or the tensilely strained layer may formed by chemical vapor deposition. The wavelength of the surface roughness may be greater than 10 nanometers (nm).
In another aspect, the invention features a structure including a compressively strained semiconductor layer having a strain greater than or equal to 0.25% and a tensilely strained semiconductor layer disposed over the compressively strained layer. The compressively strained layer is substantially planar, having a surface roughness characterized by at least one of (i) an average roughness wavelength greater than an average wavelength of a carrier in the compressively strained layer and (ii) an average roughness height less than 10 nm.
One or more of the following features may also be included. The compressively strained layer may include a group IV element, such as at least one of silicon and germanium. The strain of the compressively strained layer may be greater than 1%. The compressively strained layer may have a thickness of less than 500 Å, including less than 200 Å. The wavelength of the surface roughness may be greater than 10 nm. The tensilely strained layer may include silicon.
The compressively strained layer may include at least one of a group III and a group V element. For example, the compressively strained layer may include indium gallium arsenide, indium gallium phosphide, and/or gallium arsenide.
The compressively strained layer may include at least one of a group II and a group VI element. For example, the compressively strained layer may include zinc selenide, sulphur, cadmium telluride, and/or mercury telluride.
The structure may also include a first transistor formed over the compressively strained layer. The first transistor may include a first gate dielectric portion disposed over a first portion of the compresssively strained layer, a first gate disposed over the first gate dielectric portion, the first gate comprising a first conducting layer, and a first source and a first drain disposed proximate the first gate and extending into the compressively strained layer. The first transistor may be an n-type metal-oxide-semiconductor field-effect transistor and the first source and first drain may include n-type dopants. The first transistor may be a p-type metal-oxide-semiconductor field-effect transistor and the first source and first drain may include p-type dopants.
The structure may also include a second transistor formed over the compressively strained layer. The second transistor may include a second gate dielectric portion disposed over a second portion of the compresssively strained layer, a second gate disposed over the second gate dielectric portion, the second gate including a second conducting layer, and a second source and a second drain disposed proximate the second gate and extending into the compressively strained layer. The first transistor may be an n-type metal-oxide-semiconductor field-effect transistor, with the first source and first drain including n-type dopants, and the second transistor may be a p-type metal-oxide-semiconductor field-effect transistor, with the second source and second drain including p-type dopants.

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