Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate
Reexamination Certificate
2000-10-18
2003-05-06
Loke, Steven (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having junction gate
C438S192000, C438S195000, C438S196000
Reexamination Certificate
active
06558996
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Field of the Invention
This invention relates to a static induction semiconductor device, particularly, a static induction semiconductor device including a one conduction-type semiconductor substrate, a one conduction-type epitaxial growth layer formed on a surface of the substrate, plural concave portions which extend from a surface of the epitaxial growth layer to the substrate and define plural one main electrode regions composed of the epitaxial growth layer, plural opposite conduction-type gate regions embedded in the respective channel regions between the adjacent concave portions, plural opposite conduction-type guard regions, each being formed under each concave portion, the other main electrode regions formed on the other surface of the semiconductor substrate, and plural opposite conduction-type field limiting rings surrounding the one main electrode regions, the plural channel regions, the plural gate regions and the plural guard regions.
2) Description of the Prior Art
The above-mentioned sort of static induction semiconductor device is known as a buried gate type static induction thyristor, for example.
FIGS. 1-5
are cross sectional views showing successive steps to manufacture such a gate type static induction thyristor (SIThy). Herein, the manufacturing steps of one thyristor on a wafer will be described. First of all, as shown in
FIG. 1
, p-type impurities are implanted into a surface of an i-type (intrinsic) silicon substrate or a n
−
-type silicon substrate
111
at a predetermined energy and dose rate via a given mask, and are driven in to form P
+
-type regions
112
to constitute a guard region and, subsequently, a field limiting ring in a given pattern. Next, p-type impurities are implanted via a given mask, and driven in to form P
+
-type regions
113
, which subsequently constitute a gate region. Herein, the junction of the P
+
-type regions
112
is formed deeper than that of the P
+
-type regions
113
.
Subsequently, as shown in
FIG. 2
, an n-type epitaxial growth layer
114
is formed on the silicon substrate
111
. In this case, the p-type impurities of the p+type regions
112
and
113
are diffused into the epitaxial growth layer
114
. Thereafter, as shown in
FIG. 3
, an n
+
type surface layer
114
′ is formed on the n-type epitaxial growth layer
114
by the conventional diffusion method.
Next, as shown in
FIG. 4
, the epitaxial growth layer
114
having the n
+
type surface layer
114
′ is selectively etched on its surface, and thereby, concave portions
115
is so formed to extend to the P
+
type regions
112
. Channels
116
are composed of the sandwiched portions of the silicon substrate
111
by the adjacent concave portions
115
. Then, one main electrode regions, n-type cathode regions
117
in this example, are formed from the sandwiched portions of the epitaxial growth layer
113
, and guard regions
118
are composed of the p
+
type regions
112
. Moreover, at the same time of the formation of the concave portions
115
, large region concave portions
119
are formed by etching the epitaxial growth layer
114
covering the channels, and thereby, field limiting rings
120
, composed of the p
+
type regions
112
, are formed.
Moreover, as shown in
FIG. 5
, a silicon oxide film
121
is formed on the epitaxial growth layer
114
, and the portions of the silicon film
121
above the n-type cathode regions
117
and the p
+
type guard regions
118
are selectively removed to form cathode electrodes
122
and the gate electrodes
123
. And then, on the other surface of the silicon substrate
111
are formed n-type regions
124
, n
+
-type regions
125
and p
+
-type regions
126
. The p
+
-type regions
126
constitute anode electrode regions as the other main electrode regions, and an anode electrode
127
is formed on the whole back surface of the silicon substrate
111
so as to be connected to the anode electrode regions. At the outside of the field limiting rings
120
are formed channel stop rings
128
having electrodes
129
thereon composed of the n-type epitaxial growth layer
114
.
During operation of the SIThy, a direct current power supply is connected between the cathode electrodes
122
and the anode electrode
127
, such that a forward main voltage is applied therebetween. If the thyristor is switched-on, positive signals for the gate electrode
123
to cathode electrodes
122
are input into. Just then, a main current is flown from the anode electrode
127
to the cathode electrodes
122
via channels
116
. And, if a negative gate bias voltage for the cathode electrodes is applied to the cathode electrodes
122
, electric charges are extracted from the gate electrodes
123
, and thereby, the depletion region is enlarged from the gate regions
112
and the guard regions
118
. As a result, the electric conduction through the channels
116
is shut down and no current is flown between the anode electrode
127
and the cathode electrodes
122
. In this off-state, although the main voltage is applied between the anode electrode
127
and the cathode electrodes
122
, the thyristor can have a large voltage-resistance because its electric field intensity is mitigated by the guard regions
118
and the field limiting rings
120
in the cathode electrode side.
In the conventional embedded gate type SIThy as mentioned above, the large concave portions
119
to form the regions including the field limiting rings
120
are formed in the forming step of the concave portions
115
which are elongated between the surface of the epitaxial growth layer
114
and the silicon substrate and define unit segments S in the cathode side. The concave portions
115
and
119
are formed by wet-etching using a mixed solution of hydrofluoric acid, nitric acid, acetic acid and so on. However, if the concave portions
119
is formed by the above wet-etching, they tend to have their shallow central portions as shown in FIG.
6
. For example, although the concave portion
119
shown in
FIG. 6
has a depth D
1
of almost 17 &mgr;m at both ends, it has a depth D
2
of only almost 14 &mgr;m at its central portion, which is smaller than the depth D
1
by 3 &mgr;m.
If the concave portion
119
does not have uniform depth over its whole region, the n-type epitaxial growth layer
114
partially remains at the upper sides of the field limiting rings
120
, resulting in the difficulty of the whole spread of a depletion layer
130
. That is, if the n-type regions exist on the spreading region of the depletion layer
130
, the edge of the depletion layer is unlikely to spread and thus, a current field is concentrated at a smaller region than a predetermined region. As a result, a desired forward blocking voltage ability, that is, high blocking voltage can not be realized in the thyristor.
The cause of the shallow central portion of the concave portion
119
shown in
FIG. 6
in the forming step of the field limiting ring
120
using wet-etching will be considered below.
In wet-etching, an etching solution is stirred and an additional etching solution is supplied constantly in order to perform the uniform etching process. In this case, the etching process is hindered if the gases generated in the above etching process are adsorbed on a surface of a material to be etched. In view of the above matter, Japanese registered utility model No. 1,827,697 discloses the technique of supplying the etching solution to the material from above in an oblique direction. If the etching solution is supplied from above in an oblique direction, the active etching reactive solution, including many etching species incorporated in the etching solution, is easily supplied to the edge portions of the concave portion to be formed because the edge portions are adjacent to the non-etched regions. On the other hand, the reaction-ended inactive etching reactive solution tends to stay at the central portion of the concave portion because the etching reaction occurs
Burr & Brown
Loke Steven
NGK Insulators, Inc.
LandOfFree
Edge structure for relaxing electric field of semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Edge structure for relaxing electric field of semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Edge structure for relaxing electric field of semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3001666