Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate
Reexamination Certificate
2000-08-15
2002-05-28
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having junction gate
C438S238000, C438S384000
Reexamination Certificate
active
06395590
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to semiconductor integrated circuits. In particular, the present invention pertains to an integrated circuit including a nonvolatile memory and a capacitor used as an analog device.
BACKGROUND OF THE INVENTION
It is often desirable to provide both memory circuitry and analog circuitry on the same integrated circuit. One such desirable integrated circuit may include a nonvolatile memory, such as an EPROM, EEPROM or flash memory, and a so-called low voltage coefficient capacitor. A low voltage coefficient capacitor is a capacitor whose capacitance and/or resistance does not significantly vary with an applied voltage. This is an important characteristic for analog applications and it primarily determines the performance of analog circuits. For example, a parasitic capacitor formed from a depletion region is generally not considered to be a low voltage coefficient capacitor because the capacitance value of such a capacitor is a function of the depletion region, which in turn, is sensitive to the applied voltage. An example of a low voltage coefficient capacitor includes two polycrystalline silicon (poly) capacitor plates separated by a dielectric layer. For both polysilicon electrode plates, the doping level should be very high to avoid the degradation of capacitor voltage coefficient due to the contribution of parasitic depletion capacitance inside the polysilicon films.
FIG. 1
shows a prior art plate capacitor. This capacitor has a top-poly-electrode
15
and a bottom-poly-electrode
13
having an edge
19
. As shown, the electrodes
15
and
13
are offset such the edge
19
of bottom-poly-electrode
13
is overlapped by top-poly-electrode
15
. Further, this prior art plate capacitor includes substrate
10
(e.g., having an n
−
conductivity), a contact diffusion region
11
(e.g., having a p
+
conductivity), a field oxide region
12
, a dielectric capacitor
14
, an interlayer dielectric
18
, metal contact regions
16
, and a passivation layer
17
(e.g., formed of glass). The configuration of
FIG. 1
provides simple connection of metal contacts to each electrode
15
and
13
without risk of short circuit between the electrodes
15
and
13
.
For most of the common nonvolatile memory processes, double polysilicon films are utilized for the memory cells—the first polysilicon for the floating gate and the second polysilicon (normally with metal silicide on top) for the control gate. Unfortunately, the first polysilicon is usually lightly doped to ensure the quality and reliability for the gate oxide beneath the floating gate and for the interpoly dielectric (e.g. ONO layer) between the floating gates and control gates. As a result, with the second polysilicon as the bottom electrode plate and interpoly capacitor, the additional third polysilicon film has to serve as the top electrode plate. In other words, the complicated triple polysilicon process becomes inevitable for the embedded non-volatile memory products in analog applications.
However, formation of such a poly capacitor can be difficult in certain applications.
FIGS. 2-6
illustrate a proposed manner of forming such a device. Illustratively, the device formed includes one or more nonvolatile memory cells similar to those designed by Silicon Storage Technologies™. See U.S. Pat. No. 5,242,848. First, a field oxide
12
is formed, e.g., using the well-known LOCOS (local oxidation of silicon) process. According to such a process, a nitride layer such as Si
3
N
4
is deposited on the Si substrate
10
, and windows are patterned in the nitride layer in the vicinity at which the field oxide regions are to be formed. The substrate is then heated in the presence of oxygen.
Next, a gate oxide region
14
is deposited or grown on the substrate
10
surface. Then, a first poly layer
16
(poly
1
) is deposited on the gate oxide
14
. As shown in
FIG. 3
, the poly layer
16
is patterned to form poly floating gates
18
. The poly floating gates
18
typically must be lightly doped. Referring to
FIG. 4
, poly oxides
20
are grown on the poly floating gates
18
using a second LOCOS step. A thin oxide having dielectric spacers
22
(such as SiO
2
, Si
3
N
4
or ONO) are also formed on the side surfaces of the poly floating gates
18
. Then, a second poly layer
24
(poly
2
) is deposited on the substrate, i.e., so as to cover the spacers
22
, field oxide
12
and poly oxide
20
, and gate oxide
14
. A metal silicide may also be formed on the poly
2
layer
24
(not shown).
As shown in
FIG. 5
, the second poly layer is patterned to form control gates
26
on the poly oxides
20
and one of the spacers
22
of each cell. The patterning step also forms a bottom or lower capacitor plate
28
on the field oxide
12
. A dielectric layer
30
, such as a chemical vapor deposition (CVD) tetraethylorthosilicate (TEOS), CVD-ONO, or other high dielectric materials (e.g., Ta
2
0
5
, etc.) is then deposited on the substrate surface so as to cover the lower capacitor plate
28
, field oxides
12
and
20
, control gates
26
, spacers
22
and gate oxide
14
. Then, a third poly layer
32
(poly
3
) is formed on the dielectric layer.
As shown in
FIG. 6
, the poly
3
layer
32
is patterned to form the top or upper capacitor plate
34
. Then, the dielectric layer
30
is patterned to form the dielectric region
36
on the capacitor plate
28
. Additional steps may be performed for forming the source and drain regions of the memory cells
38
, which are not described herein.
The above proposed process for fabricating the combined nonvolatile memory cell and capacitor, however, is difficult to implement for several reasons. First, as shown in
FIG. 5
, the dielectric layer
30
is applied directly on top of the exposed portions of the gate oxide
15
in peripheral CMOS devices. The dielectric layer
30
is patterned by etching away the unwanted portions of the dielectric layer
30
using a wet etchant. As shown in
FIG. 7
, this can undercut the oxide
14
in a vicinity of a CMOS gate
40
.
More importantly, the overall topographical height by which the memory cell structures protrude from the substrate surface make it very difficult to pattern the poly
3
layer in forming the upper capacitor plate. This is illustrated in
FIGS. 8 and 9
.
FIG. 8
shows an overhead view of a nonvolatile memory cell formed according to the prior art.
FIG. 9
shows a cross section through the line A—A′ after the poly
3
layer
32
and dielectric layer
30
have been deposited and prior to patterning the upper capacitor plate and dielectric region. This corresponds to the highest topological height or profile of the substrate prior to the patterning of the poly
3
layer
32
. As can be seen, part of the floating gate
18
and poly oxide region
20
overlie a field oxide region
42
. In order to describe the topographical issues more clearly, each file thickness is assigned to have a typical value. Here, the average thickness of the poly
3
layer
32
is about a=2700 Å. The average thickness of the dielectric layer
30
(in this example, a CVD-TEOS material) is b=450 Å. The average thickness of the poly
2
control gate
26
is c=3200 Å. The average thickness of the middle of the gate poly oxide region
20
is d=2200 Å. The average thickness of the middle of the floating gate
18
is 500 Å. The height of the field oxide region
42
above the gate oxide layer
14
(which is the lowest point on the substrate surface to which the poly
3
layer
32
and the dielectric layer
30
must be etched) is f=3000 Å.
In patterning the poly
3
layer
32
and the dielectric layer
30
, a photoresist material is coated onto the substrate surface. A light beam is then passed through a photolithographic mask which exposes selected portions of the photoresist to the light beam. The non-exposed portions of the photoresist material are then removed. The remaining photoresist portions act as a mask to protect the underlying region
Lebentritt Michael S.
Luu Pho M.
Proskauer Rose LLP
Winbond Electronics Corporation
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