Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate
Reexamination Certificate
2011-03-22
2011-03-22
Pham, Hoai v (Department: 2892)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having junction gate
C438S188000, C257SE21043
Reexamination Certificate
active
07910417
ABSTRACT:
A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.
REFERENCES:
patent: 4700461 (1987-10-01), Choi et al.
patent: 4959697 (1990-09-01), Shier et al.
patent: 5198879 (1993-03-01), Ohshima
patent: 6020607 (2000-02-01), Nagai
patent: 6097046 (2000-08-01), Plumton
patent: 6111423 (2000-08-01), Imoto
patent: 6125046 (2000-09-01), Jang et al.
patent: 6271550 (2001-08-01), Gehrmann
patent: 6542001 (2003-04-01), Yu
patent: 7605412 (2009-10-01), Hower et al.
patent: 2002/0008260 (2002-01-01), Yamazaki et al.
patent: 2003/0117825 (2003-06-01), Liaw et al.
patent: 2004/0222475 (2004-11-01), Hao et al.
Hower Philip L.
Lin John
Merchant Steven L.
Walch David A.
Brady III Wade J.
Franz Warren L.
Pham Hoai v
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Distributed high voltage JFET does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Distributed high voltage JFET, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Distributed high voltage JFET will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2691393