Mitigation of edge degradation in ferroelectric memory...

Mixed metal nitride and boride barrier layers

Mixed mode process

Mixed mode process for embedded dram devices

Mixed voltage CMOS process for high reliability and high...

Mixed-mode process

Mixed-mode process

Mixed-signal semiconductor platform incorporating...

Mobility enhancement by strained channel CMOSFET with single...

Modified film stack and patterning strategy for stress...

Modified gate processing for optimized definition of array...

Modified gate processing for optimized definition of array...

Modified nitride spacer for solving charge retention issue...

Modified source/drain re-oxidation method and system

Modified zero layer align method of twin well MOS fabrication

Monos device having buried metal silicide bit line

Monotonic dynamic-static pseudo-NMOS logic circuit and...

MOS device and method of fabricating the same

MOS device having non-uniform dopant concentration and...

MOS device with dual gate insulators and method of forming...