Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-04
2001-03-06
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S286000, C438S289000
Reexamination Certificate
active
06197627
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a MOS device and a method of fabricating the same and, more particularly, to a MOS device of a structure suitable for use in the control system of a satellite to be launched into space and the control system of a nuclear reactor, and capable of reducing leakage current that occurs at the edges of element isolation regions isolating the elements of the MOS device when the MOS device is exposed to gamma rays or the like.
2. Description of the Prior Art
A MOS (Metal-Oxide-Semiconductor) device using a semiconductor substrate, having a semiconductor layer on top of an insulation film formed on a supporting substrate, namely, SOI (Silicon on Insulator) substrate, is well known.
The MOS device using the SOI substrate is known to have an advantage in that it can achieve complete electrical insulation and isolation among the elements, thus suppressing a latch up phenomenon.
Furthermore, the MOS device having the thin semiconductor layer formed on the insulation film is effective in preventing the short channel effect and enhancing its current driving capacity because the majority of the electric charge in the depletion layers is dominated by the potential of its gates.
Referring to
FIGS. 49 and 50
, the structure of a conventional MOS device is described hereafter.
FIG. 50
is a plan view showing a form of such a MOS device and
FIG. 49
is a cross sectional view taken on line X—X in FIG.
50
.
As shown in
FIG. 49
, in the MOS device, an SOI substrate
4
, consisting of a supporting substrate
1
, an insulation film
2
, and a semiconductor layer
3
patterned in a plurality of islands, is in use.
The MOS device comprises an n-channel semiconductor device
11
and a p-channel semiconductor device
12
, wherein a gate oxide film
14
and a gate electrode
8
(see
FIG. 50
) are formed on top of a channel region
7
of respective islands of the semiconductor layer
3
formed on the SOI substrate
4
. More specifically, the n-channel semiconductor device
11
is an N MOS FET (field effect transistor) and the p-channel semiconductor is a P MOS FET; both are combined to form a MOS device, constituting a complementary MOS-IC.
In the figures, only one unit of the MOS device is shown, however, a large number of the MOS devices of an identical structure (Complementary MOS-ICs) are normally formed on a single SOI substrate.
As shown in
FIG. 50
, each island of the semiconductor layer is provided with a source
6
and a drain
5
in regions on the opposite sides of the gate electrode
8
of the semiconductor layers
3
of the MOS device.
The respective islands of the semiconductor layer
3
formed on the SOI substrate
4
are completely insulated and isolated from each other by an interlayer dielectric film
32
formed around each of the islands of the semiconductor layer
3
; interconnections
33
a
,
33
b
, and
33
c
, each having one end connected to the source
6
, the drain
5
, and the gate electrode
8
, respectively, through contact holes
21
formed in the interlayer dielectric film
32
, are provided; the other end of each interconnection
33
a
,
33
b
, and
33
c
being connected to the source
6
, the drain
5
, and the electrode
8
, respectively, of the other MOS device formed on the same SOI substrate.
In the MOS device using the SOI substrate described as above, parasitic MOS regions
9
are formed, as shown in
FIG. 49
, by each island of the semiconductor layer
3
; the edges of the element isolation regions, that is, the boundaries between the island of the semiconductor layer
3
and the interlayer dielectric film
32
formed around the peripheries of the islands of the semiconductor layer
3
; and, the gate electrodes
8
formed over the edges of the element isolation regions.
In each of the parasitic MOS regions, a MOS structure consisting of the gate oxide film
14
and the gate electrode
8
is formed in a direction perpendicular to the channel region
7
of the n-channel semiconductor device
11
and the p-channel semiconductor device
12
, respectively, on the boundary between each island of the semiconductor layer
3
and the interlayer dielectric
32
.
In the parasitic MOS region, a channel is induced by an electric field of lower intensity than that for a normal channel region because, in this region, an electric field created by a normal channel region
7
(on top of the surface of the semiconductor layer
3
) and an electric field created by a MOS structure formed on the sidewalls of the island of the semiconductor layer
3
are added together. As a result, a leakage current occurs.
Now, referring to
FIG. 51
, a conventional MOS device of an improved type so as to prevent the occurrence of leakage current in the parasitic MOS region
9
is described hereafter.
FIG. 51
is a cross sectional view, similar to
FIG. 49
, showing the improved conventional MOS device.
In this case, a boundary region film
15
, thicker than the gate oxide film
14
, is formed in the peripheral regions of respective islands of the semiconductor layer
3
between respective gates
8
and respective islands of the semiconductor layer
3
. By virtue of the boundary region film
15
, the intensity of an electric field created in the parasitic MOS region is modulated, reducing leakage current.
Referring to
FIGS. 52 and 53
, the correlation between the thickness of a gate oxide film and radiation exposure dose is described.
FIGS. 52 and 53
indicate the correlation between radiation exposure dose and variation in the threshold voltage with varying thickness of the gate oxide film of a MOS device as a parameter;
FIG. 52
represents the case of an n-channel semiconductor device and
FIG. 53
a p-channel semiconductor device. In
FIGS. 52 and 53
, the horizontal axis indicates gamma ray exposure dose and the vertical axis indicates variation in the threshold voltage (&Dgr;Vth) caused by radiation exposure.
As is evident from these figures, as radiation exposure dose increases, so does the magnitude of variation in the threshold voltage in the case of both the n-channel semiconductor device and p-channel semiconductor device; furthermore, the thicker the gate oxide film, the more pronounced the trend of the increase in the threshold voltage becomes.
Also, it is apparent that the electric charge of the substance in the gate oxide film is of positive polarity in view of the threshold voltage shifting in the negative direction. In other words, the thicker the gate oxide film, the greater the magnitude of variation in the threshold voltage with respect to a radiation exposure dose.
Accordingly, when the MOS device of the structure as described in
FIG. 51
is used as a radiation-resistant semiconductor device, the thicker the gate oxide film, the greater the positive electric charge that builds up when the device is exposed to radiation.
In the semiconductor device as shown in
FIG. 51
, the boundary region film
15
, namely, an oxide film, for both the n-channel semiconductor device
11
and the p-channel semiconductor device
12
, is formed much thicker than the gate oxide film
14
in order to modulate the intensity of the electric field created in the parasitic MOS region
9
.
When this semiconductor device is exposed to radiation, positive holes of electron-hole pairs created by the radiation are trapped at the energy level of the atoms constituting the gate oxide film, causing positive electric charge to occur.
As shown in
FIGS. 52 and 53
, the thicker the gate oxide film, the greater the magnitude of such positive electric charge. Thus, in the semiconductor device of the structure as shown in
FIG. 51
, the boundary region film
15
, consisting of an oxide film thicker than the gate oxide film
14
, ends up having a greater positive electric charge than the gate oxide film
14
.
As a result, in the n-channel semiconductor device
11
, leakage current increases in the parasitic MOS region
9
because the threshold voltage of the parasitic MOS region becomes lower than for the channel region
7
, although ther
Armstrong, Westerman Hattori, McLeland & Naughton
Citizen Watch Co. Ltd.
Meier Stephen D.
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