Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-08
2001-07-10
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S270000
Reexamination Certificate
active
06258644
ABSTRACT:
FIELD OF THE INVENTION
The invention is generally related to the field of MOSFET transistors and more specifically to a novel process to achieve high performance core transistor performance and high I/O transistor reliability with reduced mask steps.
BACKGROUND OF THE INVENTION
For mixed voltage technologies, e.g. low voltage core transistors with operating voltages of about 1.8 volts to 1.2 V and high voltage input-output (I/O) transistors with operating voltages of about 3.3 volts to 2.5 volts, it is difficult to achieve both high reliability and high performance for both the core transistors and the I/O transistors without adding extra mask steps to independently optimize the core transistors and the I/O transistors.
The higher operating voltages of the I/O transistors make them susceptible to hot carrier degradation. To reduce this effect, a lightly doped drain (LDD) or drain extension is utilized. In this disclosure, LDD will be used to represent any drain extension type implant. The drain extension typically extend the heavily doped source and drain regions further under the gate of the transistor. In some applications, this LDD is formed using a low dose, high energy arsenic implant which results in acceptable reliability for the high voltage NMOS I/O transistor. In an effort to reduce masking steps, this low dose, high energy arsenic implant can also be used to form the LDD structure in the low voltage core NMOS transistor. However, this LDD structure will significantly degrade the core NMOS transistor drive current (I
drive
), most notably, as the drain supply voltage (VDD) for the core is scaled down from about 1.8 volts to about 1.2 volts. This drive current degradation is most probably due to the increase in the series resistance (R
s
R
d
) present in the source and drain and the associated LDD structure. As the drain supply voltage is reduced, the drive current will become increasingly limited by the this series resistance.
Thus the LDD structure required for achieving high reliability in the high voltage NMOS I/O transistors will severely degrade the I
drive
in the low voltage NMOS core transistors due to high series resistance R
s
R
d
and damage from the high energy arsenic implant. Present integrated circuit fabrication methodologies necessitates the use of additional masking steps to separately optimize both transistors. There is therefore great need for a reduced masking step process that will optimize both transistors and result in both high reliability and high performance without the high cost associated with increased masking steps.
SUMMARY OF THE INVENTION
The instant invention is a mixed voltage CMOS method for high reliability and high performance core and input-output transistors with reduced masks.
An embodiment of the instant invention is a method of making a reliable NMOS input-output transistor comprising the steps of: forming at least one region of a second conductivity type in a semiconductor substrate of a first conductivity type; forming a gate dielectric of a first thickness on said semiconductor substrate; forming a gate dielectric of a second thickness on said semiconductor substrate wherein said gate dielectric of a second thickness is equal to or thicker than said gate dielectric of a first thickness; forming a first conductive layer on said gate dielectric of a first thickness; forming a second conductive layer on said gate dielectric of a second thickness; etching said first conductive layer and said gate dielectric of a first thickness to form a first transistor gate stack on said semiconductor substrate of a first conductivity type; etching said first conductive layer and said gate dielectric of a first thickness to form a second transistor gate stack on said semiconductor substrate of a second conductivity type; etching said second conductive layer and said gate dielectric of a second thickness to form a third transistor gate stack on said semiconductor substrate of a first conductivity type; simultaneously implanting said first transistor gate stack and said third transistor gate stack with a first implant of a first species type; simultaneously implanting said first transistor gate stack and said third transistor gate stack with a second implant of a second species type; simultaneously implanting said second transistor gate stack and said third transistor gate stack with a third implant of said first species type; and simultaneously implanting said second transistor gate stack and said third transistor gate stack with a fourth implant of said second species type. Preferably, the first conductivity type is p-type and the second conductivity is n-type. The first implant species type is comprised of a material selected from the group consisting of: B, BF2, Ga, In, and any combination thereof, and the second species type is comprised of a material selected from the group consisting of: As, P, Sb, and any combination thereof.
Another embodiment of the instant invention is a method of fabricating a mixed voltage integrated circuit, comprising the steps of: forming at least one region of a second conductivity type in a semiconductor substrate of a first conductivity type opposite said second conductivity type; forming a gate dielectric on said semiconductor substrate; forming a conductive layer on said gate dielectric; etching said conductive layer and said gate dielectric to form a first transistor gate stack on said semiconductor substrate and a second transistor gate stack on said one region of said second conductivity type; and simultaneously implanting said first transistor gate stack and said second transistor gate stack with a pocket implant for said first transistor gate stack whereby said pocket implant for said first transistor gate stack functions as LDD implant for said second gate stack.
An advantage of the instant invention is that no masking steps are required for forming the mixed voltage integrated circuits. Another advantage of the instant invention is that no additional implants are required other than those required for forming the core transistors. Another advantage of the instant invention is that the pocket implant of one transistor device type will be used as the drain extension of the other transistor device type.
These and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.
REFERENCES:
patent: 5416736 (1995-05-01), Kosa et al.
patent: 5465001 (1995-11-01), Skotnicki et al.
patent: 5932918 (1999-08-01), Krakauer
patent: 6075271 (2000-06-01), Smith
Mehrotra Manoj
Nandakumar Mahalingam
Rodder Mark S.
Brady III W. James
McLarty Peter K.
Nelms David
Nhu David
Telecky , Jr. Frederick J.
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