Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-10
2004-06-29
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S201000, C438S211000, C438S263000, C438S264000
Reexamination Certificate
active
06756268
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of semiconductor manufacture and, more particularly, to a modified source/drain re-oxidation process.
As computers become increasingly complex, the need for memory storage, and in particular the number of memory cells, increases. At the same time, there is the need to minimize the size of computers and memory devices. A goal of memory device fabrication is to increase the number of memory cells per unit area or wafer area.
Memory devices contain blocks or arrays of memory cells. A memory cell stores one bit of information. Bits are commonly represented by the binary digits 0 and 1. A conventional non-volatile semiconductor memory device in which contents can be electrically programmable or simultaneously erased by one operation is a flash memory device.
Flash memory devices have the characteristics of low power and fast operation making them ideal for portable devices. Flash memory is commonly used in portable devices such as laptop or notebook computers, digital audio players and personal digital assistant (PDA) devices.
In flash memory, a charged floating gate is zero logic state, typically represented by the binary digit 0, while a non-charged floating gate is the opposite logic state typically represented by the binary digit 1. Charges are injected or written to a floating gate by any number of methods, including avalanche injection, channel injection, Fowler-Nordheim tunneling, and channel hot electron injection, for example.
The key performance parameters of a flash memory cell are programming rates, erase rates, and data retention. These parameters are a strong function of the post source drain re-oxidation gate edge profile. This profile is also referred to as a reox smile. During source drain re-oxidation, the thickness of the tunnel oxide and oxide-nitride-oxide (ONO) layers are increased along the exposed edge of the gate electrodes. The profile of this thickness enhancement plays a major role in the performance of a flash memory cell. As the thickness of this profile increases, reliability and data retention increases while erase rates or speeds worsen. Thus, it is desirable to accurately control the thickness of this profile. However, there are only limited ways to modify this profile. A common way to attempt to modify the profile is controlling the conditions of the re-oxidation. The conditions controlled are source and drain doping concentration profiles before oxidation. However, this approach is limited.
Enhancing the ability to control this source drain re-oxidation gate edge profile is desirable.
SUMMARY OF THE INVENTION
A method that can be used to modify the smile profile during the fabrication of semiconductor devices, such as flash memory, is disclosed. A memory cell structure is defined on a substrate. A layer of phosphorous-doped oxide is deposited over substrate. Horizontal surfaces of the layer of phosphorous-doped oxide are selectively removed while vertical surfaces of the phosphorous-doped oxide remain. The horizontal surfaces are substantially planar to the substrate surface. The vertical surfaces are substantially perpendicular to the substrate surface.
A method for fabricating a flash memory cell is disclosed. A self align source is formed on a substrate. A drain is formed on the substrate. A layer of phosphorous-doped oxide is deposited on the substrate. Portions of the phosphorous-doped oxide layer are removed leaving remaining portions of the phosphorous-doped oxide layer. Standard re-oxidation is performed on the substrate.
A semiconductor device is disclosed. The semiconductor device includes a substrate, a drain, a self aligned source, a first oxide layer, a first polysilicon layer, a second dielectric layer, a second polysilicon layer and a phosphorous doped oxide layer. The drain is formed in the substrate. The self align source is formed in the substrate. The first oxide layer is deposited in the substrate from the drain to the self align source. The first polysilicon layer is deposited over the first oxide layer. The second dielectric layer is deposited over the first polysilicon layer. The second polysilicon layer is deposited over the second oxide layer. A phosphorous-doped oxide layer is located only along edges of the first oxide layer, the first polysilicon layer, the second oxide layer and the second polysilicon layer.
Other methods and devices are disclosed.
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Benistant Francis
Hurley Kelly
Rudeck Paul J.
Luu Chuong Anh
Micro)n Technology, Inc.
Smith Matthew
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