Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-05-05
2002-07-09
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S265000, C438S303000, C438S305000
Reexamination Certificate
active
06417046
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the manufacture of semiconductor devices, and in particular, to a method of forming a modified nitride spacer for solving charge retention problem in a floating gate memory cell.
(2) Description of the Related Art
Spacers are used for several different purposes in the manufacture of semiconductor devices, among them for structural as well as electrical and programmability reasons. A well-known structural use, shown in
FIGS. 1
a
-
1
f
, is in the manufacture of field effect transistors (FETs), which are also very well-known for their very small size, high packing density in the Ultra Scale Integration (ULSI) technology. Employing conventional methods, gate-oxide layer (
30
) is first formed over substrate (
10
) having already defined active regions bounded by passive field oxide regions (
20
) shown in
FIG. 1
a
. A polysilicon layer is blanket deposited over the substrate and etched to form poly-gate (
40
), as shown in
FIG. 1
b
. Gate-oxide other than that underlying the poly-gate is also etched away. Using poly-gate as a self-aligned mask, ion implantation is usually employed to form source and drain regions (
15
). Subsequently, an oxide layer (not shown) is formed over the substrate and anisotropically etched, following conventional methods, to form oxide spacers (
50
) shown in
FIG. 1
c.
One of the early structural uses of oxide spacers such as shown (
50
) in
FIG. 1
d
was in forming self-aligned silicide (SAC) contacts, which are well-known in the art. Thus, after the forming of the spacers, metal used to form the silicide is deposited over the substrate. The substrate is then heated, which causes the silicide reaction to occur wherever the metal is in contact with the silicon. Everywhere else, the metal remains unreacted. The unreacted metal is selectively removed through the use of an etchant that does not attack the silicide, the silicon, or the oxide. As a result, each exposed source and drain region is now completely covered by silicide film (
60
), out there is no film elsewhere. A dielectric layer, (
70
), is next deposited onto the silicide, and contact holes are opened in it down to the silicide layer following conventional techniques (
FIG. 1
e
). Metal (
80
) is deposited into the contact holes to make contact with the silicide, which provides excellent electrical characteristics. Thus, the oxide spacers have performed the structural function of separating silicided areas from shorting each other, and also, as it will be known to those skilled in the art, providing tapered holes for making good tapered self-aligned silicide (SAC) contacts.
However, spacers (
50
) on the sidewall of gates, hence sometimes called sidewall spacers, also provide an important function in aligning ion implants which in turn control electron flow to and fro between the floating gate and the channel in the semiconductor substrate. In
FIG. 1
f
, which is redrawn from
FIG. 1
d
, the length of the space bounded by the source/drain regions (
15
) under poly-gate (
400
) is defined as the channel length (
13
) of the FET. As the advances in ultra scale integration continues, the channel length is further reduced resulting in undesirable short channel effects (SCE). This is due to the fact, as it will be known to those skilled in the art, that the band gap and built-in potential at junctions are an intrinsic property (constant) of the crystalline materials (such as silicon), and are non-scalable with the further reduction in device dimensions. One of the SCE effects exhibits itself, what is known as the hot carrier effect (HCE). This is where electrons ejected from the drain area can acquire sufficient energy to be injected into the gate oxide resulting in charge buildup in the oxide that causes threshold voltage shifts. Unfortunately, HCE is known to severely degrade the performance of FET devices.
One common method of minimizing these short channel effects is to fabricate FET structures with Lightly Doped Drains (LDDs), actually, including the source regions also. These LDD structures are formed using sidewall spacers, such as shown in
FIG. 1
f
, and two implants. The LDDs serve to absorb some of the potential into the source/drain (S/D) regions and thus reduce the maximum electric field. One of these implants is self-aligned to the gate electrode, and forms lightly doped S/D regions (
15
) shown in
FIG. 1
f
. The purpose of the first implant dose is to produce lightly doped section of the drain at the gate edge near channel (
13
). The heavier second implant is self-aligned to spacers (
50
), and forms a low resistivity region (
17
) of the S/D regions, which are also merged with the previously formed lightly doped regions (
15
), as seen in
FIG. 1
f
. Since the heavily doped regions (
17
) are further away from the channel than would be the case in a conventional structure without the LDD, the depth of the heavily doped region can be made somewhat greater without adversely impacting the device operation. The increased junction depth lowers both the sheet resistance and the contact resistance of source/drain regions.
In prior art, sidewall spacers are also used to form the lightly doped S/Ds, or LDDs, by solid-phase diffusion from a doped oxide source that is also used as the sidewall spacers. Thus, doped side-wall spacers are formed by depositing a doped oxide (e.g., phosphosilicate glass (PSG)) and anisotropically etching as shown in
FIG. 1
f.
After implanting the source/drain contact areas (
17
) (N
+
), the substrate is annealed to drive in the dopant to form the lightly doped source/drain areas (
15
) (N
−
) and to activate and anneal out the implant damage in the N
+
source/drain areas. However, the LDD regions (
15
) now extend further under the poly-gate, or gate electrode (
40
) such that the effective length of channel (
13
) is considerably reduced, sometimes by about one-half the original length of the channel. Thus, for an FET with a 0.2 &mgr;m gate width, the effective channel length could be only about 0.1 &mgr;m. In other words, gate electrode (
40
) significantly overlays the out diffused lightly doped S/D regions (
15
) resulting in high gate-to-drain capacitance that degrades the RC delay time, as it will be known to those skilled in the art. Also, the LDD S/D regions extending significantly under the gate electrode results in unwanted short channel effects, such as hot carrier injection in the gate oxide.
Huang of U.S. Pat. No. 5,989,966 proposes a method for suppressing such short channel effects by forming gate oxide on a substrate and patterning a polysilicon to form a gate electrode; forming first spacers comprising silicon nitride on the sidewalls of the gate electrode; forming second sidewall spacers from a doped oxide that serve as a solid-phase diffusion source; implanting S/D regions adjacent second sidewall spacers; annealing the substrate to diffuse dopant from the second sidewall spacers to form the lightly doped S/D regions; thus using the first silicon nitride spacers to serve as a diffusion barrier so that the LDDs formed under the gate electrode do not intrude as much into the channel area under the gate electrode. And hence, the reduced gate-to-drain overlay capacitance and improved immunity to hot electron effects.
Another method for achieving increased resistance to hot carrier damage with the use of sidewall spacers is disclosed by Aminzadeh, et al., in U.S. Pat. No. 5,827,769. Here, an oxide is grown on the gate electrode. This oxide s strengthened by nitridation and anneal. After a light doped drain implant, a second side oxide and a conformal nitride layer are deposited. Then, the conformal nitride is anisotropically etched to form spacers for masking a high dose drain implant. An NMOS transistor fabricated with this process has been found to be forty percent less susceptible to hot carrier damage than a conventional LDD process.
In another U.S. Pat. No. 5,966,606, a sidewall spacer formed through nitridation of the gate electr
Chang Chuan-Li
Chen Hsin-Ming
Chu Wen-Ting
Ho Ming-Chou
Kuo Di-Son
Dang Trung
Oktay Sevgin
Taiwan Semiconductor Manufacturing Company
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