Modified zero layer align method of twin well MOS fabrication

Details Modified zero layer align method of twin well MOS fabrication Modified zero layer align method of twin well MOS fabrication

1996-10-28

1999-02-02

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438199, 438401, 438228, H01L 218238

Patent

active

058664475

ABSTRACT:
A method for fabricating alignment marks in a twin-well integrated circuit without using a zero-layer photomask is disclosed. This method involves the steps of: (a) forming a pad oxide layer on a P-type semiconductor wafer; (b) obtaining an N-well photomask containing an N-well pattern for defining an N-well region in the P-type semiconductor wafer and an alignment mark pattern for defining a plurality of alignment marks in the P-type semiconductor wafer, the N-well photomask is designed such that the alignment mark pattern and the N-well pattern can be separately exposed; (c) using a photolithography technique to expose only the alignment mark pattern to form a plurality of the alignment marks in the pad oxide layer and the P-type semiconductor wafer; (d) coating a first photoresist layer overlaying the pad oxide layer which is aligned using the alignment marks formed in step (b); (e) using the N-well photomask to pattern the first photoresist layer and define the N-well region; and (f) ion-implanting N-type impurities to form the N-well region in the P-type semiconductor wafer.

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