Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-02-15
2003-11-18
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S201000, C257S302000, C257S315000, C257S334000
Reexamination Certificate
active
06649476
ABSTRACT:
TECHNICAL FIELD
The invention relates to CMOS gate arrays. The invention also relates to vertical ultrathin body transistors. The invention further relates to monotonic dynamic-static pseudo-NMOS logic circuits.
BACKGROUND OF THE INVENTION
CMOS technology is used for digital integrated circuits due to low power dissipation, high density of integration, and low cost of fabrication. CMOS technology is also used for analog integrated circuits.
Applications that use microelectronic components, such as telecommunications equipment, industrial control equipment, automotive electronics, etc., require more and more specialized integrated circuits. The continuing development in semiconductors has led to use of gate arrays and standard cells as a modern and inexpensive way to produce Application Specific Integrated Circuits (ASICs). An ASIC is an integrated circuit that can place on a single chip an entire system or a great part of it, performing not only digital, but also analog functions.
Gate arrays are used in ASIC design. A CMOS gate array can be described as a matrix of premanufactured (e.g., identical) cells that only requires the addition of the final metal and contact masks to define a new circuit function. Gate array technology can thus quickly respond to customer requirements in a low cost and efficient manner. Gate arrays can be implemented using a variety of circuit and process technologies including static CMOS and bipolar emitter coupled logic.
FIG. 1
shows a prior art static CMOS logic circuit
10
. A problem with static CMOS logic circuits is that each input
12
and
14
must drive two gates, the gate of one NMOS transistor and the gate of a PMOS transistor. Input
12
drives gates
16
and
18
, and input
14
drives gates
20
and
22
. This results in a large area for static CMOS circuits and a large number of metal wiring levels must be utilized to allow interconnections.
Another problem with static CMOS logic circuits is that in the PMOS transistor the hole mobility is about three times lower than the mobility of electrons if the transistors have comparable sizes. Because of this, switching transients are very asymmetrical. The charge up transient of the capacitive load in a simple inverter takes far longer than the discharge transient. To attempt to compensate, the PMOS transistors are often fabricated with a large width or size to provide symmetrical switching. However, this increases the stray capacitive loads and results in an even larger area for the circuits, and very inefficient area utilization.
REFERENCES:
patent: 4569032 (1986-02-01), Lee
patent: 4797580 (1989-01-01), Sunter
patent: 5525916 (1996-06-01), Gu et al.
patent: 5550487 (1996-08-01), Lyon
patent: 5691230 (1997-11-01), Forbes
patent: 5796282 (1998-08-01), Sprague et al.
patent: 5798938 (1998-08-01), Heikes et al.
patent: 5828234 (1998-10-01), Sprague
patent: 5867036 (1999-02-01), Rajsuman
patent: 5942917 (1999-08-01), Chappell et al.
patent: 5973514 (1999-10-01), Kuo et al.
patent: 5977579 (1999-11-01), Noble
patent: 6072209 (2000-06-01), Noble et al.
patent: 6077745 (2000-06-01), Burns, Jr. et al.
patent: 6107835 (2000-08-01), Blomgren et al.
patent: 6108805 (2000-08-01), Rajsuman
patent: 6150687 (2000-11-01), Noble et al.
patent: 6399979 (2002-06-01), Noble et al.
patent: 6406962 (2002-06-01), Agnello et al.
patent: 6448601 (2002-09-01), Forbes et al.
patent: 6496034 (2002-12-01), Forbes et al.
patent: 2002/0109173 (2002-08-01), Forbes et al.
patent: 2003/0025712 (2003-02-01), Corr
patent: 0 082 773 (1982-12-01), None
T. Thorp. G. Yee and C. Sechen, “Monotonic Static CMOS and Dual VT Technology”, Sym. Low Power Electronics and Design, San Diego, 16-17 Aug. 1999, pp 151-155.
T. Thorp, G. Yee, and C. Sechen, “Domino logic synthesis using complex static gates,” IEEE/ACM Int. Conf. On Computer-Aided Design, pp. 1. 1998.
P. Kalavade et al, A Novel Sub-10nm Transistor, IEEE Device Research Conf., Denver, Co, Jun. 2000, pp. 71-72.
P. Xuan et al.,60nm Planarized Ultra-thin Body Solid Phase Epitaxy MOSFETs, IEEE Device Research Conf., Denver, Co, Jun. 2000, pp. 67-68.
Bernstein, Kerry, et al., “High-Speed Design Styles Leverage IBM Technology Prowess”, 6 pages (Aug. 22, 1999).
Hergenrother, J.M., et al., “The Vertical Replacement-Gate (VRG) MOSFET: A 50-nm Vertical MOSFET with Lithography-Independent Gate Length”,IEEE#0-7803-5413, 4 pages (Mar. 1999).
Lebentritt Michael S.
Luu Pho
Micro)n Technology, Inc.
Wells St. John P.S.
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