Mixed mode process for embedded dram devices

Details Mixed mode process for embedded dram devices Mixed mode process for embedded dram devices

1999-10-29

2001-06-05

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06242300

ABSTRACT:

BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method for forming an embedded DRAM device with a mixed mode capacitor.
2) Description of the Prior Art
Two of the major classifications of devices manufactured by the semiconductor industry are logic and memory. Logic devices are used primarily to process information, while memory devices are used for information storage. Traditionally, while these two device types are found in virtually all electronic systems, such as computers and the like, they have been manufactured on separate integrated circuits and connected only at the card or board level. This has been due to differences in manufacturing processes, cost considerations, economies of scale, and other difficulties in fabricating different device structures on the same substrate.
However, trends in the semiconductor industry are driving toward making it both desirable and feasible to blend memories and logic on the same integrated circuit (IC). The process for combining logic and memory on the same IC is called an embedded process. Cost and performance are the two key factors contributing to these trends. While significant economies of scale can be realized by separate batch processing of large numbers of semiconductor wafers for the two types of device, due to the different process steps needed to produce them, cost savings can also be realized by forming logic and memory on the same IC. For example, an embedded process IC requires decreased area as compared to separate ICs because of the elimination of input/output pins, wiring, etc, thereby, increasing yield and reducing cost.
Performance enhancements may also make blending logic and memory on the same IC attractive for particular applications. In electronic systems in which logic and memory are packaged separately, data signals between the two may have to pass through several layers of packaging (i.e. through the original IC chip to external pins, then through the card and/or board wiring, and finally into the receiving IC chip including its internal wiring) all of which cause undesirable propagation delays. As device densities have increased and device sizes have decreased, transistor switching speeds no longer limit the logic delay or access time of the IC, Rather, the time for the device to charge capacitive loads is the limiting factor for IC performance. The capacitive load is partially dependent on the length of lines interconnecting devices, and so minimizing these connection lengths, as through combining logic and memory on the same IC, will enhance performance.
It is also desirable to integrate mixed-mode capacitors with the logic and memory on the same IC. Capacitors are a basic building block for many electronic circuits, and may be used for analog applications such as switched capacitor filters, or for digital applications such as the storage node for a dynamic random access memory (DRAM). Traditionally, formation of a capacitor requires separate photo masks for the bottom electrode and the top electrode. Photo masks are a significant cost driver in IC fabrication.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,866,451 (Yoo et al.) shows a method for forming a
4
T SRAM and mixed mode capacitor in logic.
U.S. Pat. No. 5,719,079 (Yoo et al. al.) shows a method for forming a
4
T SRAM and mixed mode capacitor in logic with a salicide process.
U.S. Pat. No. 5,702,988 (Liang) shows a process for forming an embedded device.
U.S. Pat. No. 5,605,853 (Yoo et al.) shows a method for forming a
4
T SRAM and floating gate memory cells.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for forming a mixed mode capacitor in an embedded DRAM process.
It is another object of the present invention to provide a method for forming a mixed mode capacitor in an embedded DRAM process with a minimum quantity of photo masks.
It is yet another object of the present invention to provide an embedded DRAM process which forms a mixed mode capacitor, provides polycide and hard mask for the memory gates, and provides titanium silicide source and drain contacts, and contacts for the logic gates.
To accomplish the above objectives, the present invention provides a method for forming an embedded DRAM device with a mixed mode capacitor in the logic. The process begins by providing a semiconductor structure having a logic area and a memory area. The logic area and the memory area are separated by an isolation structure, and the logic area has a second isolation structure thereon. A first dielectric layer is formed over the semiconductor structure, and a first polysilicon layer is formed on the first dielectric layer. The first polysilicon layer and the gate dielectric layer are patterned to form an opening over the memory area. In a key step, an implant mask is formed over the first polysilicon layer with an opening over the second isolation structure, and impurity ions are implanted into the first polysilicon layer through the opening in the implant mask. After the implant mask is removed, a second dielectric layer is formed over the semiconductor structure and the first polysilicon layer. A second polysilicon layer is formed on the second dielectric layer; a silicide layer is formed on the second polysilicon layer; and a hard mask layer is formed on the silicide layer. The second polysilicon layer, the silicide layer, and the hard mask layer are patterned to form a bottom electrode for a mixed mode capacitor over the second isolation structure in the logic area and gates in the memory area. The first polysilicon layer is patterned to form gate structures in the logic area.
The present invention provides considerable improvement over the prior art. The present invention provides a method for forming an embedded DRAM device with a mixed-mode capacitor requiring only one additional photo mask compared to the inventors' current embedded DRAM process. Also, the present invention provides a method for forming an embedded DRAM device having polycide and a hard mask for the DRAM gates and titanium silicide source and drain contacts for the logic gates.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.


REFERENCES:
patent: 5605853 (1997-02-01), Yoo et al.
patent: 5702988 (1997-12-01), Liang
patent: 5719079 (1998-02-01), Yoo et al.
patent: 5866451 (1999-02-01), Yoo et al.
patent: 6004841 (1999-12-01), Chang et al.
patent: 6030872 (2000-02-01), Lu et al.
patent: 6103622 (2000-08-01), Huang
patent: 6117725 (2000-09-01), Huang

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