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High voltage transistor using P+ buried layer

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High voltage transistor using P+ buried layer

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High voltage transistor using P+ buried layer

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High voltage transistor with high gated diode breakdown voltage

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High voltage transistor with high gated diode breakdown, low bod

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High voltage transistors with graded extension

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High withstand voltage semiconductor device and manufacturing me

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High withstand voltage transistor and method for manufacturing t

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High write and erase efficiency embedded flash cell

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High yield performance semiconductor process flow for NAND...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High yield semiconductor device and method of fabricating...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High-capacitance density thin film dielectrics having...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High-capacitance dynamic random access memory cell and method fo

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High-density germanium-on-insulator photodiode array

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High-density metal capacitor using dual-damascene copper...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High-density nonvolatile memory cell

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High-density split-gate FinFET

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High-dielectric constant insulators for FEOL capacitors

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High-dielectric constant insulators for FEOL capacitors

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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High-k dielectric bird's beak optimizations using...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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