High-k dielectric bird's beak optimizations using...

Details High-k dielectric bird's beak optimizations using... High-k dielectric bird's beak optimizations using...

2003-03-25

2004-06-08

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S595000, C438S225000, C438S230000, C438S504000, C438S452000

Reexamination Certificate

active

06746925

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to processes for fabricating semiconductor devices. More particularly, the present invention relates to the use of plasma oxidation to reduce lateral encroachment during the fabrication processes.
2. Description of the Related Art
Semiconductor wafer fabrication involves a series of processes used to create semiconductor devices and integrated circuits (ICs) in and on a semiconductor wafer surface. Fabrication typically involves the basic operations of layering and patterning, together with others such as doping, and heat treatments. Layering is an operation used to add thin layers of material (typically insulator, semi-conductor or conductor) to the surface of the semiconductor wafer. Patterning is an operation that is used to remove specific portions of the top layer or layers on the wafer surface. Patterning is usually accomplished through the use of photolithography (also known as photomasking) to transfer the semiconductor design to the wafer surface.
As the scaling of the Metal Oxide Semiconductor (MOS) transistor proceeds toward deep sub-micron dimensions, high-k gate dielectric materials (which are defined as materials that can provide a k value significantly higher than that of SiO
2
) are becoming more predominant in replacing silicon dioxide (SiO
2
) as a gate dielectric. One problem with SiO
2
gate dielectrics is excessive leakage current at the sub-90 nm process nodes.
However, one of the issues related to using high-k materials as gate dielectrics is the formation of bird's beak encroachment at the corner edge of the gate stack due to lateral encroachment of the formed SiO
2
under the high-k material. The bird's beak encroachment typically has a tapered shape. The formation of the SiO
2
bird's beak directly under the corner of the gate electrode (such as Poly-Si) will significantly reduce the effective k-value and thereby increase the gate equivalent oxide thickness (EOT). Such bird's beak encroachment is thus unacceptable for CMOS transistor manufacturing.
Conventional approaches to mitigating the encroachment include physical sputter etching of high-k dielectrics. The sputter etching will re-deposit high-k dielectric into the sidewall of the gate stack to minimize the high-k dielectric's etch undercut, and thus, reduce the high-k dielectric's bird's beak formation directly under the gate electrode. However, it is difficult to control the thickness of the re-deposited layer of high-k dielectric. Moreover, it may not be possible to completely eliminate the SiO
2
encroachment directly under gate electrode with this technique.
Accordingly, it is desirable to provide a more effective process for controlling the SiO
2
encroachment from directly under the active gate electrode.
SUMMARY OF THE INVENTION
To achieve the foregoing, the present invention provides a process that provides increased control of gate sidewall oxide layers and prevents oxide encroachment from being formed under the gate electrode. The poly gate electrode layer is deposited and etched, with the etching stopping on the high-k material layer. Oxidation of the sidewall of the gate electrode stack is achieved using in-situ O
2
plasma oxidation. Thus, the sidewall oxide thickness can be controlled by varying the O
2
plasma and oxidation time parameters. A high-k dielectric layer etch follows using plasma dry etching, thus avoiding etching of the high-k material under the sidewall due to the anisotropic nature of the plasma etch.
In one embodiment, the present invention provides a process for forming a gate dielectric while minimizing lateral encroachment of a SiO
2
layer. A dielectric layer is deposited on a substrate. A gate electrode layer is formed on the dielectric layer. The gate electrode layer is patterned and etched. An oxidized layer is formed on the sidewalls of the gate electrode stack using plasma oxidation. The exposed oxidized layer is then etched using a plasma dry etch. The plasma oxidized areas are then removed.
In another embodiment, thickness of the oxidized layer is controlled by controlling to a predetermined value at least one of the oxidation time and plasma process parameters. Control of the plasma oxidation is further obtained by applying a higher RF power to the top portion of a plasma reactor while applying a lower RF value to the bottom portion of the plasma reactor.
In yet another embodiment, the dielectric layer is one of hafnium oxide, hafnium silicate, aluminum oxide, zirconium oxide, and other metal oxides that contain one, two or even more cations and nanolaminate layers.


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