High-capacitance dynamic random access memory cell and method fo

Details High-capacitance dynamic random access memory cell and method fo High-capacitance dynamic random access memory cell and method fo

1996-03-15

1998-04-07

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438595, H01L 218242

Patent

active

057364419

ABSTRACT:
A semiconductor structure for a DRAM cell having a high capacitance capacitor. The DRAM cell includes a silicon substrate on which a field oxide layer and a transistor having a gate layer and a source/drain region are formed. A contact surface is formed on a surface of the source/drain region. A silicon nitride layer is formed over the gate layer. A thick oxide layer is formed over one part of the silicon nitride layer, at a lateral side of the contact surface. Silicon nitride spacers are formed over opposite lateral sides of the gate layer, the silicon nitride layer, and the thick oxide layer. One of the silicon nitride spacers located adjacent to the contact surface, is shaped in the form of a pointed protrusion. A self-aligned contact insulating layer covers the thick oxide layer and the other silicon nitride spacer, that is located away from the contact surface. This structure defines a jagged surface over at least the contact surface, the pointed protrusion and the silicon nitride layer. A high surface area capacitor structure, including a first conductive layer, a dielectric layer over the first conductive layer, and a second conductive layer over the dielectric layer, is then formed over the jagged surface.

REFERENCES:
patent: 5061650 (1991-10-01), Dennison et al.
patent: 5478769 (1995-12-01), Lim
patent: 5550078 (1996-08-01), Sung
patent: 5554557 (1996-09-01), Koh

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