Scalable set/reset circuit with improved rise/fall mismatch
Scan cell designs for a double-edge-triggered flip-flop
Scan circuit having a reduced clock signal delay
Scan flip-flop circuit
Scan flip-flop circuit capable of guaranteeing normal operation
Scan flip-flop that holds state during shifting
Scan flip-flop with power saving feature
Scan testable double edge triggered scan cell
Scannable latch
Scannable latch
Scannable master slave latch actuated by single phase clock
Scanner circuit for digital signals with high data rate
Scheme for controlling rise-fall times in signal transitions
Scheme for delay locked loop reset protection
Scheme for reducing leakage current in an input buffer
Scheme to improve performance of timing recovery systems for...
Schmidt trigger circuit
Schmidt trigger circuit having sensitivity adjusting...
Schmitt circuit
Schmitt trigger circuit